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Mixed Signal FPGAs (ADC/DAC) - MLE FPGA IP Core Design
MLE’s Mixed-Signal FPGA technology further broadens the application space from pure digital protocols to so-called “amplitude-modulated” protocols which require plenty of configurable analog I/Os embedded inside proven off-the-shelf FPGA devices.
By Missing Link Electronics
ML/AI Essentials for Hardware Engineers
This foundational course provides hardware engineers, FPGA designers, and embedded software engineers with the machine learning and deep learning knowledge required to participate effectively in AI hardware acceleration projects.
By FPGA Authority
Modbus TCP/IP Server Subsystem for Altera FPGA
Modbus TCP/IP Server for Altera FPGA provides an optimized Switch IP Core and a Communication Processor for the Integration of Modbus TCP/IP and other industrial networks into field devices. It uses the same API for all supported protocols.
By Softing Industrial
Modern DC-SCM-compliant datacenter engineering services with Antmicro Open Hardware Modular Agilex® 5 DC-SCM Carrier Board
The open hardware Agilex® 5 Modular DC-SCM Carrier Board, designed to support the Agilex® 5 E-Series FPGAs and to be in accordance with the OCP DC-SCM 2.1 standard, offers a flexible and widely adoptable solution for server management. With programmable FPGA logic combined with embedded dual-core Cortex A55 and dual-core Cortex A76, as well as the ability to switch Agilex® 5 E-Series modules, it can be customized to fit specific applications and scale even further with the help of Antmicro’s engineering services, including customization of the OpenBMC Linux distribution.
By Antmicro
MPEG2 Video Decoder
Fabric only, MPEG2 Decoder IP core HD60 Decoding supporting interlaced and progressive.
By System-On-Chip Technologies Inc.
MPEG2 Video Encoder
Legacy MPEG2 Video Encoder IP core Supporting HD Progressive and Interlaced formats Runtime API
By System-On-Chip Technologies Inc.
MSC-CTRL Microsecond Channel high-speed controller
The MSC-CTRL IP core implements a high-speed serial interface controller designed to connect an SoC to external power devices or sensors. It implements the Microsecond Channel (MSC) protocol and acts as a bus master for downstream and as a bus slave for upstream transfers. The MSC-CTRL is integrated to peripherals via high-speed synchronous downstream and low-speed asynchronous upstream channels. It supports up to four slave devices in the MSC mode, advanced features, fragmented command frames, and higher upstream baud rates, provide robust communication in a network of dedicated sensors or devices. The IP includes a 32-bit AMBA® APB4 subordinate interface and includes trigger signals to facilitate easy integration with an external DMA controller. The silicon-proven MSC-CTRL core is designed to industry best practices and has been rigorously verified. Optional functional safety documents facilitate ISO 26262 ASIL B standard.
By Computer Aided Software Technologies, Inc (dba CAST)
Multi User NVMe IP core for Gen4 (muNVMe-IP)
muNVMe-IP (Multi-user NVMe IP) is designed and optimized for simultaneous access to a single NVMe™ SSD by multiple data streams. It delivers near-maximum SSD throughput for both mixed and same-direction read/write operations. Ideal for applications requiring high performance and multiple data streams or sequential access via pure hardware logic without CPU or OS.
By DesignGateway Co., Ltd.
Multi-Algorithm SHA3 Hash Engine IP Core (SHA3-IP)
SHA3-IP is a fully offload hash engine by hardware logic, ideal for high-throughput applications requiring secure communications and data integrity.
By DesignGateway Co., Ltd.