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Multi-point Input / Output Expander, Altera Cyclone® FPGA Design
Multi-point Input / Output Expander, Altera Cyclone® FPGA Design
By Orchid Technologies Engineering and Consulting, Inc.
Multi-Rate Ethernet PHY FPGA IP
The Multi-Rate Ethernet PHY FPGA IP core can dynamically support multiple data rates from 10M to 10GbE in accordance with the IEEE 802.3 Ethernet Standard without any design regeneration or device reconfiguration.
By Altera
Multichannel DMA IP for PCI Express
Accelerate designs with Multichannel DMA for PCIe IP – fast and efficient data movement, flexible features, and Linux driver support.
By Altera
MyMENSCH™ - W65Cx65MMC10M08 Development Board
SBC/Development board based on MAX10M08SA
By WDC
N-EMB-100 ZEKE EtherCAT Master_Slave
The N-EMB-100 platformThe N-EMB-100 is a high-performance industrial device platform equipped with an Cyclone® V SoC. It has two Arm Cortex-A9 processor cores and can use Linux, etc. in SMP mode. It has four RJ45 connectors: two ports for Arm-side Gigabit Ethernet and two ports for FPGA-side EtherCAT. Since it is equipped with two 10/100 PHYs on the FPGA side, it can also use Altera's TSE MAC IP, etc. QSPI or microSD cards can be used as boot memory, and the boot source can be selected with jumpers on the board. This board can be used in a variety of EtherCAT (hardware master/software master and slave) applications.Hardware Master: You can evaluate our hardware master using the Ethernet on the FPGA side.Software Master: You can implement various paid software masters using the Ethernet on the Arm side. We can also provide a demo environment with an open-source master stack implemented.Slave: It can also be used as a slave by implementing an EtherCAT slave IP, such as one made by BECKH
By NDR Co.,LTD.
N-EMB-110 ZEKE-G EtherCAT Master_Slave
The N-EMB-110 is a high-performance industrial device platform equipped with a Cyclone® V SoC. It has two Arm Cortex-A9 processor cores and can use Linux, etc. in SMP mode. It has four RJ45 connectors: two ports for Arm-side Gigabit Ethernet and two ports for FPGA-side EtherCAT. It also has four USB ports available. Since it is equipped with two 10/100/1000 PHYs on the FPGA side, it can also use Altera®'s TSE MAC IP, etc. QSPI or microSD cards can be used as boot memory, and the boot source can be selected with jumpers on the board. This board can be used in a variety of EtherCAT (hardware master/software master and slave) applications.Hardware Master: You can evaluate our hardware master using the Ethernet on the FPGA side.Software Master: You can implement various paid software masters using the Ethernet on the Arm side. We can also provide a demo environment with an open-source master stack implemented.Slave: It can also be used as a slave by implementing an EtherCAT slave IP, such
By NDR Co.,LTD.
N-EMB-120 OSCAR EtherCAT Master_Slave
The N-EMB-120 is a high-performance industrial platform featuring MAX®10 FPGAs. MAX 10 has a built-in sufficient RAM capacity, and since you can use FLASH for both config ROM and ROM, you can realize a custom CPU with one chip by using Nios® II. It is equipped with external SDRAM (32MByte x 16bit) and QSPI FLASH (521Mbit), but it can also be expanded according to the software application capacity. Since two 10/100 PHYs are installed on the FPGA side, it is possible to use Altera's TSEMAC IP. The board can be used in a variety of EtherCAT (hardware master and slave) applications. Hardware master: It is possible to evaluate our hardware master. It was developed as a retrofit to the existing CPU board to realize "Instant EtherCAT". Slave: It can also be used as a slave by mounting BECKHOFF's EtherCAT slave IP on the Ethernet on the FPGA side.
By NDR Co.,LTD.
N-EMB-500 RUFE ASSP BOARD
N-EMB-500-A/B is an evaluation platform for developing in-house ASSPs and dealing with discontinued ICs. It features the MAX® 10 10M08SA FPGA, which can operate on a single 3.3V power supply and has a built-in configuration ROM, enabling single-chip FPGA operation. The MAX® 10 FPGA supports dual-boot configuration and can implement Nios II processors. You can also utilize the analog functions of the MAX® 10 FPGA to manage the board's power sequencing and power management. General-purpose LEDs, DIP switches, and push switches can be freely controlled from the MAX® 10 FPGA through HDL coding.Features when combined with a baseboard:Built-in USB Blaster II: You can start development immediately without needing a separate FPGA programming device (USB Blaster II). Simply connect a USB cable between your PC and the baseboard to perform operations equivalent to a USB Blaster II. This allows programming the FPGA, GUI-based FPGA control using the System Console, and internal FPGA signal analysis
By NDR Co.,LTD.
NAND Flash Controller
The iWave NAND Flash Controller IP Core enables efficient and secure access to SLC and MLC NAND memory with built-in ECC, bad block management, and wear-leveling. It is ideal for FPGA-based storage, boot, and logging applications requiring high data integrity and flexibility.
By iWave Global
