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PTP Hybrid Clock (IEEE1588 – Precision Time Protocol)
Full standalone hardware only solution of a PTP Hybrid Clock (Combined PTP TC and OC)
By NetTimeLogic GmbH
PTP Ordinary Clock (IEEE1588 – Precision Time Protocol)
Full standalone hardware only solution of a PTP Ordinary Clock
By NetTimeLogic GmbH
PTP Timestamp Unit (IEEE1588 – Precision Time Protocol)
PTP Timestamp Unit
By NetTimeLogic GmbH
PTP Transparent Clock (IEEE1588 – Precision Time Protocol)
Full standalone hardware only solution of a PTP Transparent Clock
By NetTimeLogic GmbH
Q-Box v2
Network cybersecurity appliance designed specifically for critical infrastructure and OT systems in retrofit or greenfield deployments. Provides a quantum and AI resistant base for a Zero Trust network architecture through cryptographically enforced micro-segmentation.
By Q-Net Security, Inc.
QECIPHY - Free Open Source physical layer implementation
The physical layer of QECi (QECIPHY) allows data to be sent reliably between a control system and a QEC system. Our implementation of QECIPHY is available open source and can be easily integrated with any FPGA-based platform.
By Riverlane
Quality+ IP - 1:10 video compression preserves image SNR
Gidel’s Quality+ (Q+) IP targeting FPGA compresses Color Filter Array (CFA – e.g., Bayer), Monochrome, and RGB images and videos in real-time. Q+ revolutionizes image compression, achieving up to 1:10+ compression ratios for high-bandwidth image streams while preserving original image quality.The Quality+ IP can be embedded seamlessly in Gidel's image acquisition systems, including the Gidel frame grabbers and compact edge computers. The compression supports high-end camera streaming, including 10+ GigE Vision, CoaXPress and Camera Link. Gidel's real-time compression IPs are particularly beneficial for high-bandwidth and high-resolution imaging and vision applications enabling to improve image quality while increasing recording time, reducing storage size, and reducing post recording data offload and compression time on host computer.
By Gidel
Quartus Design Software Fundamentals
This course provides engineers with a practical introduction to the Altera® FPGA primary development environment, Quartus Prime.
By FPGA Authority
Quartus Software Debug
This course provides a comprehensive, structured approach to debugging software running on Altera SoC devices.
By FPGA Authority