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Quartus Software Debug
This course provides a comprehensive, structured approach to debugging software running on Altera SoC devices.
By FPGA Authority
Quartus Timing Closure Masterclass
This advanced course equips experienced FPGA engineers with the skills and methodology to achieve reliable, repeatable timing closure on complex Altera® FPGA designs using Quartus® Prime.
By FPGA Authority
QUIC Client 1Gbps IP core (QUIC1GC-IP)
QUIC (Quick UDP Internet Connections) is a modern transport layer protocol designed to overcome the limitations of TCP while providing TLS 1.3-level security. Design Gateway's fully hardware-based QUIC-IP offloads the CPU by handling TLS 1.3 handshake, payload encryption/decryption, and managing both the QUIC and UDP/IP layers. This enables secure, high-performance communication entirely through hardware logic.
By DesignGateway Co., Ltd.
QUIC Server 10Gbps IP core (QUIC10GS-IP)
QUIC (Quick UDP Internet Connections) is a modern transport layer protocol designed to overcome the limitations of TCP while providing TLS 1.3-level security. Design Gateway's fully hardware-based QUIC-IP offloads the CPU by handling TLS 1.3 handshake, payload encryption/decryption, and managing both the QUIC and UDP/IP layers. This enables secure, high-performance communication entirely through hardware logic.
By DesignGateway Co., Ltd.
R-Tile PCIe* Hard IP
R-Tile is an FPGA companion tile that supports PCI Express* configurations up to PCIe 5.0 x16 in Endpoint (EP), Root Port (RP) and Transaction Layer (TL) Bypass modes. PCIe 3.0, 4.0, and 5.0 configurations are natively supported.
By Altera
Random Access & Multi User NVMe Gen5 IP core (rmNVMe-IP)
rmNVMe-IP (Random Access & Multi-User NVMe IP) is a high-performance NVMe™ host controller optimized for high-IOPS random access applications. With pure hardware logic and no CPU involvement, it supports multiple user interfaces for simultaneous read/write access to a single NVMe SSD. Ideal for use cases like real-time sensor data fusion, OS file system offloading, and SSD testing, it offers excellent energy efficiency, performance, and low FPGA resource usage.
By DesignGateway Co., Ltd.
Random Access NVMe IP core (raNVMe-IP)
raNVMe-IP (Random Access NVMe IP) is specifically optimized for random access and low latency. It can achieve over 700K IOPS for random write access on high-performance NVMe™ SSDs without CPU intervention. This makes it ideal for applications like database search, which require frequent, high-speed access to NVMe SSDs.
By DesignGateway Co., Ltd.
RapidIO to AXI Bridge Controller (Silicon Proven IP for Altera Devices)
Mobiveil’s RIO-AXI Bridge provides a layered, configurable architecture connecting RapidIO to AXI-based systems. It includes high-speed DMA and streaming engines to meet demanding bandwidth needs. Technology-agnostic and highly integrable, it suits cost-sensitive, performance-driven designs in FPGAs and ASICs.
By Mobiveil Inc.
RDMA IP Core for RoCE v2 at 10 Gbps
GROVF RDMA IP Core for RoCE v2 enables low-latency, FPGA-based RDMA connectivity over Ethernet. The solution delivers 10 Gb/s throughput and integrates with standard Verbs API environments, helping customers build efficient, interoperable RDMA-enabled FPGA systems.
By Grovf Inc.