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Real-Time JPEG Compression IP
Gidel’s real-time JPEG image compression (encoder) IP enables high-performance JPEG compression on FPGA. The compression IP is unique in its fast processing capacity, low latency, and compact silicon utilization. As a result of its compactness, the IP can be implemented on a small FPGA device to compress high-performance camera image streams or, alternatively, instantiated multiple times on a single larger FPGA device. The JPEG IP can be embedded seamlessly in Gidel's image acquisition systems, including the Gidel frame grabbers and compact edge computers. The compression supports high-end camera streaming, including 10+ GigE Vision, CoaXPress and Camera Link. Gidel's real-time compression IPs are particularly beneficial for high-bandwidth and high-resolution imaging application enabling increased recording time, reduces storage size, and reduced post recording data offload and compression time on host computer.
By Gidel
Reed Solomon II FPGA IP Core
The Reed Solomon II IP offers a fully parameterizable Reed Solomon encoder and decoder.
By Altera
ReflexArc™ – Deterministic FPGA Co-Processor for Physical AI & Robotics
ReflexArc™ is a deterministic FPGA co-processor platform for Physical AI and robotics, combining GPU-based AI intelligence with FPGA-based real-time acceleration, sensor processing, scheduling, and control. Designed for heterogeneous GPU + FPGA systems, ReflexArc enables low-latency, predictable execution for next-generation autonomous and robotic applications.
By Levcom, Inc.
RS IP
The Reed-Solomon (RS) IP Core is a powerful and flexible Forward Error Correction (FEC) engine designed to enhance data integrity in digital communication systems. Leveraging the robust error-correcting capabilities of RS codes, this IP core ensures resilience against burst errors and improves overall system reliability across a wide range of applications including satellite communications, storage systems, digital broadcasting, and high-speed networking.
By Qbit Labs Incorporation
RTC Master (Real-Time Clock)
Full standalone hardware only solution of an RTC Master
By NetTimeLogic GmbH
RTOS Development on Altera SoC Platforms
This course is built for Altera SoC FPGA designers who want to develop deterministic, production grade real time systems using Zephyr RTOS on Altera SoC FPGA platforms.
By FPGA Authority
RunX Low-Latency H.264 Video Encoder IP Core
Low-latency, hardware-optimized H.264/AVC video encoder IP core suitable for both FPGA and ASIC implementations in real-time embedded systems.
By RunX Technology
S10PCIe-TS
The MPAC6500 (Hambledon) is a full-height, full-length PCIe Gen3 x16 FPGA packet-processing card with an Intel® Stratix® 10 FPGA and 4×100GBASE-LR4/SR4 QSFP28 interfaces.
By Terasic Inc.
SAS 1 to 1 Speed Bridge with Sandbox (IPP-SS115A-BR)
The IntelliProp IPP-SS115A-BR is a high-performance SAS 1:1 Speed Bridge with an integrated 'Sandbox' for real-time frame manipulation. It provides industry-compliant 3G, 6G, and 12G SAS connections, allowing for speed-independent bridging and hardware-accelerated data processing between SAS hosts and devices.
By IntelliProp: Experts in Memory and Data Storage IP
