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Scalable Ultra-High Throughput Image and Video Scaler
The UHT-SCALER core provides a video processing block which converts input video frames of one size and sampling format to output frames of a different size and/or sampling format.
By Alma Technologies S.A.
Scalable Ultra-High Throughput VESA DSC 1.2b Decoder
UHT-DSC-D
By Alma Technologies S.A.
Scalable Ultra-High Throughput VESA DSC 1.2b Encoder
UHT-DSC-E
By Alma Technologies S.A.
SCR: Smart Card Reader Controller
Implements an interface and controller for communicating between smart cards and host systems using a variety of standard system interfaces. The SCR supports the ISO/IEC 7816-3:2006 and EMV 4.3 specifications, which define the electrical signals and transmission protocols for smart cards (also known as integrated circuit cards). It acts as a communication controller, passing data to and from the host system and the smart card. It is fully-featured, and can activate and deactivate cards, perform cold/warm resets, handle ATR response reception, and execute other essential functions.
By Computer Aided Software Technologies, Inc (dba CAST)
SD / SDIO Host Controller 3.0
iWave’s SD/SDIO Host Controller 3.0 is a versatile IP core that enables efficient communication between embedded systems and SD/SDIO devices. With support for a wide range of SD card types and high-speed data transfer modes, it offers a reliable solution for applications requiring fast and secure data storage interfaces.
By iWave Global
SD Express IP Core
iWave’s SD Express IP Core enables efficient data transfer between host processors and SD Express storage devices, supporting PCIe Gen3 x1 interface and UHS-II/III modes. With its high-speed data transfer capabilities and seamless integration into FPGA-based systems, it offers a reliable solution for applications requiring fast and secure data storage interfaces.
By iWave Global
SD Memory Slave Controller
iWave’s SD Memory Slave Controller IP Core enables FPGAs to interface with SD memory cards in slave mode, compliant with SD Physical Layer Spec v2.0. With SPI and SD mode support, it is ideal for embedded systems requiring removable storage with minimal overhead.
By iWave Global
SDC Constraints and Analysis Masterclass
This course provides FPGA engineers with a comprehensive, hands-on mastery of Synopsys Design Constraints (SDC) authoring and static timing analysis (STA) using the Quartus® Prime Pro Edition Timing Analyzer.
By FPGA Authority
