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UDPIP-40G/50G: 40G/50G UDP/IP Hardware Protocol Stack
Implements a UDP/IP hardware protocol stack enabling high-speed LAN or point-to-point communication and media streaming up to 50 Gbps, even in processor-less SoC designs. Offloads the host CPU from UDP/IP encapsulation. All network parameters (IP addresses, UDP ports, MAC) are runtime programmable, supporting static or DHCP-assigned IP. Includes ARP for multi-access networks, ICMP ping for connectivity tests, and IEEE 802.1Q VLAN tagging. Supports up to 32 transmit and 32 receive streaming interfaces (channels), each independently configurable for IP, port, multicast address, and unicast/multicast mode. Integrates easily in SoC designs via AXI4-Stream, Avalon-ST, AHB, AXI, Avalon-MM, or Wishbone interfaces, with data exchange via streaming ports or memory-mapped registers. Ideal for real-time networking, video streaming, and industrial applications requiring low-latency, deterministic UDP/IP communication in FPGA or ASIC designs.
By Computer Aided Software Technologies, Inc (dba CAST)
UHS OPI PSRAM Controller (Silicon Proven IP for Altera Devices)
Targeted at wearables and low-power devices, Mobiveil’s UHS OPI PSRAM Controller supports AP Memory’s UHS series running up to 1066 MHz. It delivers low-power, high-frequency performance for memory subsystems with simplified interface requirements. The flexible architecture ensures precise control signal timing for seamless SoC integration.
By Mobiveil Inc.
Ultra Ethernet Interconnect IP for AI Infrastructure
Ultra Ethernet interconnect IP for AI infrastructure, delivering high-throughput 400G+ networking with RDMA support and advanced congestion management capabilities.
By DynaNIC Semiconductors s.r.o.
Ultra Stable Micro Kelvin Temperature Measurement system
Ultra Stable Micro Kelvin Temperature Measurement Platform • Sub micro kelvin accuracy and stability • Compatible with cost efficient NTC and PT100 sensors • Ultra low noise ADC front end for exceptional signal integrity • Real time digital signal processing and temperature computation implemented as a high performance FPGA IP core
By Kendrion 3T
Ultra-high-throughput WiFi LDPC Decoder
XCEL ASICs’ Ultra-High-Throughput Wi-Fi LDPC Decoder IP is an IEEE 802.11n/ac/ax/be–compliant (Wi-Fi 4/5/6/7) forward error correction (FEC) solution optimized for current and next-generation Wi-Fi transceivers and SoC designs. In addition to supporting earlier Wi-Fi generations, the IP enables Wi-Fi 7 (IEEE 802.11be) data rates exceeding 30 Gbps while delivering exceptional throughput-per-area efficiency, enabling very high decoding performance within a minimal silicon footprint. This combination of scalable throughput and area efficiency makes the IP particularly well suited for cost- and power-constrained, high-performance Wi-Fi transceiver chip implementations.
By XCEL ASICs LLC
Ultra-precise sub-nanometer distance-measurement system
The ultra-precise sub-nanometer distance-measurement system is built around capacitive (CAP) sensors and a low-cost Altera Cyclone 10 LP FPGA. Its exceptional resolution and accuracy make it a compelling alternative to interferometric systems in demanding high-tech applications, but at a significantly lower cost.
By Kendrion 3T
Ultrahigh Definition 4K Video Processing, Altera Agilex® FPGA Solution Using VIP
Ultrahigh Definition 4K Video Processing, Altera Agilex® FPGA Solution Using VIP
By Orchid Technologies Engineering and Consulting, Inc.
Understanding Device Architecture
This course is offered as core material followed by two independent optional sessions. The core material provides the essential, device family agnostic foundation every engineer needs before working with any Altera FPGA or SoC FPGA.
By FPGA Authority
Universal Net Red (UNR) Complete Network redundancy solution as combination of our IP cores
All in one Network Redundancy solution
By NetTimeLogic GmbH
