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This JPEG Encoder IP is compact and very efficient, capable of encoding in real-time video on-the-fly using standard and ubiquitous JPEG compression, even on low-cost FPGAs. This IP does not require any processor nor any external memory. The compression level (quality) is adjustable in real time. The compressed output is readable from any standard decoder, either Software (eg VLC, ffmpeg etc) or Hardware 'ASIC, ASSP, or FGPGA with our Decoder).
ALSE Advanced Logic Synthesis for Electronics
Key Features
- Low latency, adaptable compression, standard output, compact, image quality, no external memory
Offering Brief
Offering Brief
| Device Family | Agilex® 3 FPGA C-Series, Agilex® 5 FPGA D-Series, Agilex® 5 FPGA E-Series, Agilex® 7 FPGA F-Series, Agilex® 7 FPGA I-Series, Agilex® 7 FPGA M-Series, Agilex® 9 FPGA Direct RF-Series, Arria® 10 GT FPGA, Arria® 10 GX FPGA, Arria® 10 SX FPGA, Arria® V GT FPGA, Arria® V GX FPGA, Arria® V GZ FPGA, Arria® V ST FPGA, Arria® V SX FPGA, Cyclone® 10 GX FPGA, Cyclone® 10 LP FPGA, Cyclone® III FPGA, Cyclone® IV E FPGA, Cyclone® IV GX FPGA, Cyclone® V E FPGA, Cyclone® V GT FPGA, Cyclone® V GX FPGA, Cyclone® V SE FPGA, Cyclone® V ST FPGA, Cyclone® V SX FPGA, MAX® 10 FPGA, MAX® V CPLD, Stratix® 10 AX FPGA, Stratix® 10 DX FPGA, Stratix® 10 GX FPGA, Stratix® 10 SX FPGA, Stratix® 10 TX FPGA, Stratix® III FPGA, Stratix® IV E FPGA, Stratix® IV GX FPGA, Stratix® V GS FPGA, Stratix® V GX FPGA |
|---|---|
| Offering Status | Production |
| Integrated Testbench | Yes |
| Intertop | Tested with standard JPEG editors and viewers |
| Latest Quartus Version Supported | 25.3.1 |
| OS Support | Windows,Linux |
| Development Language | Encrypted Verilog, Encrypted VHDL |
depends on Licensing (encrypted RTL to full source code)
Ordering Information
JPEG-E
from Direct
Documentation & Resources
Market Segment and Sub-Segments
Aerospace
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Consumer
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Defense
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Industrial
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