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Aurora 64B/66B is a lightweight and open protocol suitable for chip-to-chip, board-to-board and backplane applications using high-speed transceivers. The ALSE Aurora 64B/66B IP Core is a very compact and optimized implementation developed and verified to ensure full compatibility with the published protocol and Xilinx IP core. This ALSE IP core is available on all the Altera FPGAs that include transceivers.
ALSE Advanced Logic Synthesis for Electronics
Key Features
- All configurations are supported
Offering Brief
Offering Brief
| Device Family | Agilex® 3 FPGA C-Series, Agilex® 5 FPGA D-Series, Agilex® 5 FPGA E-Series, Agilex® 7 FPGA F-Series, Agilex® 7 FPGA I-Series, Agilex® 7 FPGA M-Series, Agilex® 9 FPGA Direct RF-Series, Arria® 10 GT FPGA, Arria® 10 GX FPGA, Arria® 10 SX FPGA, Arria® V GT FPGA, Arria® V GX FPGA, Arria® V GZ FPGA, Arria® V ST FPGA, Arria® V SX FPGA, Cyclone® V GT FPGA, Cyclone® V GX FPGA, Cyclone® V SE FPGA, Cyclone® V ST FPGA, Cyclone® V SX FPGA, Stratix® 10 AX FPGA, Stratix® 10 DX FPGA, Stratix® 10 GX FPGA, Stratix® 10 SX FPGA, Stratix® 10 TX FPGA, Stratix® V GS FPGA, Stratix® V GX FPGA |
|---|---|
| Offering Status | Production |
| Integrated Testbench | Yes |
| Design Examples Available | Yes |
| Demo | Yes |
| Intertop | with Xilinx IP |
| Latest Quartus Version Supported | 25.3.1 |
| OS Support | Windows,Linux |
| Development Language | Encrypted Verilog, Encrypted VHDL, Other |
depends on licensing scheme selected
Ordering Information
AURORA64
from Direct
Documentation & Resources
Market Segment and Sub-Segments
Aerospace
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ASIC Proto
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Consumer
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Data Center Cloud (Public, Private, Hybrid)
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Defense
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Industrial
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Medical
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Imaging
Lab/Life Sciences
Non-Imaging Patient Devices
Other Medical
Ultrasound
Video
Image
Test
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Transportation
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Non-Automotive Transportation
Transportation Infrastructure (non-charging)