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The AVB-Milan IP from ALSE incorporates the functionalities defined by the Avnu MILAN Specifications for End Stations and Bridged End Stations and it is currently available on the Altera Cyclone® V SoC FPGA family. It combines a complex FPGA Hardware design (RTL) located in the programmable side of the SoC-FPGA for the very low latency and hard real time features like Ethernet packet processing, and a Software stack that runs on the ARM Multi-Processor Core System for the complex network management protocols.
ALSE Advanced Logic Synthesis for Electronics
Key Features
- No development required, usable out of the box
Offering Brief
Offering Brief
| Device Family | Cyclone® V SE FPGA, Cyclone® V ST FPGA, Cyclone® V SX FPGA |
|---|---|
| Offering Status | Production |
| Evaluation License | Yes |
| Demo | Yes |
| Intertop | MILAN |
| Latest Quartus Version Supported | 25.3.1 |
| OS Support | Windows,Linux |
| Development Language | C/C++, Encrypted Verilog, Encrypted VHDL, Other |
Complete SW + HW IP
Ordering Information
MILAN
from Direct
