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An IP core that accepts a sampled high-bandwidth RF input stream and separates it into multiple lower-bandwidth output streams that each cover a portion of the input RF spectrum.
Bit by Bit Signal Processing LLC
Key Features
- Highly parallel
- High FMax
- Resource-efficient
- Supports non-power-of-2 channelizer bins
- Supports real-to-complex channelizers
Verilog code
Documentation
Examples
Tests that can be run by the customer
Test results
Synthesis results
Performance curves
Support
Ordering Information
BxBChan
from Direct
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