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400 Gbps DMA transfers for FPGA accelerators

DynaNIC Semiconductors s.r.o.

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DYNANIC provides a production-proven, high-performance DMA IP core for transferring data between FPGA accelerators and host memory at speeds of up to 400 Gbps.

Already deployed in customer production environments as an integral part of DYNANIC's high-speed packet processing platform, the DMA engine is also available as a standalone, licensable IP solution for integration into customer FPGA designs.

The architecture supports bidirectional data transfers, multiple DMA channels and queues, and configurable PCIe interfaces, including PCIe Gen5 x16 and multi-endpoint configurations.

Efficient packet aggregation minimizes PCIe overhead, enabling high throughput even with small packet sizes. The architecture is FPGA vendor-independent and can be adapted to different hardware platforms and application requirements.

The solution includes open-source Linux drivers and supporting tools, with DPDK integration and additional software API option...

DYNANIC provides a production-proven, high-performance DMA IP core for transferring data between FPGA accelerators and host memory at speeds of up to 400 Gbps.

Already deployed in customer production environments as an integral part of DYNANIC's high-speed packet processing platform, the DMA engine is also available as a standalone, licensable IP solution for integration into customer FPGA designs.

The architecture supports bidirectional data transfers, multiple DMA channels and queues, and configurable PCIe interfaces, including PCIe Gen5 x16 and multi-endpoint configurations.

Efficient packet aggregation minimizes PCIe overhead, enabling high throughput even with small packet sizes. The architecture is FPGA vendor-independent and can be adapted to different hardware platforms and application requirements.

The solution includes open-source Linux drivers and supporting tools, with DPDK integration and additional software API options. Customers are not required to adopt DPDK or DYNANIC's complete packet-processing platform.

The DMA technology has been validated through real-world deployments and performance measurements demonstrating 400 Gbps-class host-to-card and card-to-host transfers.

DYNANIC also provides IP integration, driver adaptation, and customization services to help customers incorporate the DMA engine into their own FPGA-based products.

Key Features

  • Production-proven FPGA DMA IP
  • Demonstrated 400 Gbps host-to-FPGA throughput
  • Configurable PCIe Gen5 interfaces and multiple endpoints
  • 512+ DMA channels/queues, configuration-dependent
  • Efficient small-packet transfers with Mbuf packing
  • Open-source Linux drivers and flexible software APIs
  • Standalone IP licensing with customization options
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Offering Brief

Offering Brief

Device Family Agilex® 7 FPGA F-Series, Agilex® 7 FPGA I-Series, Agilex® 7 FPGA M-Series
Offering Status Production
Evaluation License Yes
Design Examples Available Yes
Demo Yes
Latest Quartus Version Supported 26.1.1
OS Support Linux
Development Language Encrypted VHDL, VHDL

High-Speed FPGA DMA IP Core

Linux Drivers and Software APIs

Integration and Customization Services

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