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The L8051XC1 core implements an MCS®51-compatible microcontroller that is specially designed to match the timing and peripherals of legacy 8051 MCU-based systems. The core can be configured to execute an instruction every 12, 6, or 4 clock cycles. Architectural extensions are user-selectable, including multiple data-pointers, a multiply-division unit, and a power management unit. Furthermore, the 8051 CPU can be coupled with a wide range of peripherals matching the behavior and timing of peripherals found in legacy architectures from Intel, Philips/NXP, Siemens/Infineon, Maxim/Dallas, Texas Instruments and others. Several pre-configured versions are offered; custom variations are also available. The L8051XC1 runs legacy code, but new software development is facilitated through CAST’s on-chip debugging option, and de-bug pods that cooperate with IAR Embedded Workbench & Keil uVision™ IDEs. This product builds on CAST’s experience with hundreds of 8051 IP ...
Computer Aided Software Technologies, Inc (dba CAST)
The L8051XC1 core implements an MCS®51-compatible microcontroller that is specially designed to match the timing and peripherals of legacy 8051 MCU-based systems. The core can be configured to execute an instruction every 12, 6, or 4 clock cycles. Architectural extensions are user-selectable, including multiple data-pointers, a multiply-division unit, and a power management unit. Furthermore, the 8051 CPU can be coupled with a wide range of peripherals matching the behavior and timing of peripherals found in legacy architectures from Intel, Philips/NXP, Siemens/Infineon, Maxim/Dallas, Texas Instruments and others. Several pre-configured versions are offered; custom variations are also available. The L8051XC1 runs legacy code, but new software development is facilitated through CAST’s on-chip debugging option, and de-bug pods that cooperate with IAR Embedded Workbench & Keil uVision™ IDEs. This product builds on CAST’s experience with hundreds of 8051 IP customers going back to 1997. Designed for easy reuse in ASICs or FPGAs, the core is strictly synchronous, with positive-edge clocking (except in the optional debug & SPI modules), synchronous reset, and no internal tri-states. Representative 65nm ASIC results show the core to be conservative in its use of space, requiring just 7,900 to 20,000 gates.
Key Features
- Fully compatible with the MCS® 51 instruction set, enabling seamless execution of legacy software.
- Configurable CPU: choose 12, 6, or 4 clock cycles per machine cycle to balance performance and efficiency.
- Includes a broad set of optional peripherals like SPI, I2C, timers, DMA, and real-time clock for flexible designs.
- JTAG-based On-Chip Debug Support (OCDS) simplifies development and accelerates debugging and verification.
- Supports IAR Embedded Workbench and Keil uVision™ IDEs for easy integration with popular development tools.
- Offers up to 119 Special Function Registers, 5 I/O ports, and interrupt controller with 2–4 levels and 6–18 sources.
- Features a Power Management Unit with IDLE and STOP modes to reduce power in energy-sensitive applications.
- Optional Multiply/Divide unit, advanced external memory interface, and support for external DMA controllers.
Offering Brief
Offering Brief
| Device Family | Agilex® 3 FPGA C-Series, Agilex® 5 FPGA D-Series, Agilex® 5 FPGA E-Series, Agilex® 7 FPGA F-Series, Agilex® 7 FPGA I-Series, Agilex® 7 FPGA M-Series, Agilex® 9 FPGA Direct RF-Series, Arria® 10 GT FPGA, Arria® 10 GX FPGA, Arria® 10 SX FPGA, Arria® V GT FPGA, Arria® V GX FPGA, Arria® V GZ FPGA, Arria® V ST FPGA, Arria® V SX FPGA, Cyclone® 10 GX FPGA, Cyclone® 10 LP FPGA, Cyclone® IV E FPGA, Cyclone® IV GX FPGA, Cyclone® V E FPGA, Cyclone® V GT FPGA, Cyclone® V GX FPGA, Cyclone® V SE FPGA, Cyclone® V ST FPGA, Cyclone® V SX FPGA, MAX® 10 FPGA, Stratix® 10 AX FPGA, Stratix® 10 DX FPGA, Stratix® 10 GX FPGA, Stratix® 10 SX FPGA, Stratix® 10 TX FPGA, Stratix® III FPGA, Stratix® IV E FPGA, Stratix® IV GX FPGA, Stratix® V GS FPGA, Stratix® V GX FPGA |
|---|---|
| Offering Status | Production |
| Integrated Testbench | Yes |
| Evaluation License | Yes |
| Design Examples Available | Yes |
| Compliance | Yes |
| Latest Quartus Version Supported | 24.3.1 |
| Development Language | Encrypted Verilog, Encrypted VHDL, Verilog, VHDL |
Verilog/System Verilog, VHDL, Encrypted Verilog/System Verilog, Encrypted VHDL, r FPGA netlist
Sample integration testbench
Comprehensive documentation
Sample synthesis and simulation scripts
UVM RAL models
Ordering Information
L8051XC1
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Documentation & Resources
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