.webp){kind=small}
Ethernet MAC 10M/100M/1G/2.5G IP is a solution that enables the client to communicate data using the IEEE 802.3 standard for 10M, 100M, 1G, 2.5G speeds and is suited for use in networking equipment such as switches and routers. The Client-side interface for the IP is AXI-S and the Ethernet MAC IP comes with GMII, RGMII or MII interfaces on the PHY side. The Ethernet MAC 10M/100M/1G/2.5G IP features a compact and low latency solution, it is highly configurable and can optionally include IEEE 1588 Timestamping Unit (TSU). The Silicon agnostic Ethernet MAC IP, suitable for ASICs and FPGAs, is prepared for easy integration with Ethernet PCS 10M/ 100M/1G/2.5G IP from Comcores.
Comcores ApS
Key Features
- Designed to IEEE 802.3-2018 specification
- Low latency and compact implementation
- Full duplex Ethernet interfaces
- FCS generation and jumbo frames supported
- Optional comprehensive statistics gathering
- Independent TX and RX Maximum Transmission Unit (MTU) frame length
- Promiscuous and non-promiscuous mode
- Optional MDIO interface
- 8-bits AXI-Stream interface
- Cut-through operation mode, Store and Forward is optional
- Optional IEEE 1588 Support
- Comes with GMII as default PHY interface – MII and RGMII can be optionally selected
Offering Brief
Offering Brief
| Device Family | Agilex® 5 FPGA D-Series, Agilex® 5 FPGA E-Series, Agilex® 7 FPGA F-Series, Agilex® 7 FPGA I-Series, Agilex® 7 FPGA M-Series, Agilex® 9 FPGA Direct RF-Series, Arria® 10 GT FPGA, Arria® 10 GX FPGA, Arria® 10 SX FPGA, Arria® II GX FPGA, Arria® V GT FPGA, Arria® V GX FPGA, Arria® V GZ FPGA, Arria® V ST FPGA, Arria® V SX FPGA, Cyclone® 10 GX FPGA, Cyclone® III FPGA, Cyclone® III LS FPGA, Cyclone® IV GX FPGA, Cyclone® V GT FPGA, Cyclone® V GX FPGA, Cyclone® V SE FPGA, Cyclone® V ST FPGA, Cyclone® V SX FPGA, Stratix® 10 AX FPGA, Stratix® 10 DX FPGA, Stratix® 10 GX FPGA, Stratix® 10 SX FPGA, Stratix® 10 TX FPGA, Stratix® III FPGA, Stratix® IV GT FPGA, Stratix® IV GX FPGA, Stratix® V GS FPGA, Stratix® V GX FPGA |
|---|---|
| Offering Status | Production |
| Integrated Testbench | Yes |
| Evaluation License | Yes |
| Latest Quartus Version Supported | 24.3.1 |
| Development Language | Encrypted Verilog, Verilog |
Solid documentation, including User Manual and Release Note
Simulation Environment, including Simple Testbed, Test case and Test Script
Programming Register Specification
Timing Constraints in Synopsys SDC format
Access to support system and direct support from Comcores Engineers
Synopsys SGDC Files (optional)
Synopsys Lint, CDC and Waivers (optional)
Ordering Information
CM_ETHMAC_01_B_F
from Direct
Market Segment and Sub-Segments
Aerospace
View Sub-Segments
Data Center OEM (IHV, ISV, SI, VAR)
View Sub-Segments.svg?h=0&v=8a74a614-b7ba-4604-ad78-f0827c6a3874&itok=rVWXlOCO)
Defense
View Sub-Segments
Industrial
View Sub-Segments