The 1G deep buffering memory Ethernet Switch is an advanced Ethernet switching IP that supports buffering large amounts of data in external RAM. The switch supports MAC learning, VLAN 802.1Q, multicast and broadcast as well as IEEE 1588 transparency.
Comcores ApS
Key Features
- QoS features like classification, queuing, and priorities included
- Automatic MAC address learning and aging
- Supports buffering of up to 128 MB in DDR
- Extensive statistic reporting
- Buffer size is fully configurable
- Configurable scheduling (round-robin, strict priority, among others)
- Configurable tagging
- GMII interfaces for attaching external Physical Layer devices (PHY)
Offering Brief
Offering Brief
| Device Family | Agilex® 5 FPGA D-Series, Agilex® 5 FPGA E-Series, Agilex® 7 FPGA F-Series, Agilex® 7 FPGA I-Series, Agilex® 7 FPGA M-Series, Agilex® 9 FPGA Direct RF-Series, Arria® 10 GT FPGA, Arria® 10 GX FPGA, Arria® 10 SX FPGA, Arria® II GX FPGA, Arria® II GZ FPGA, Arria® V GT FPGA, Arria® V GX FPGA, Arria® V GZ FPGA, Arria® V ST FPGA, Arria® V SX FPGA, Cyclone® 10 GX FPGA, Cyclone® 10 LP FPGA, Cyclone® II FPGA, Cyclone® III FPGA, Cyclone® III LS FPGA, Cyclone® IV E FPGA, Cyclone® IV GX FPGA, Cyclone® V E FPGA, Cyclone® V GT FPGA, Cyclone® V GX FPGA, Cyclone® V SE FPGA, Cyclone® V ST FPGA, Cyclone® V SX FPGA, MAX® 10 FPGA, Stratix® 10 AX FPGA, Stratix® 10 DX FPGA, Stratix® 10 GX FPGA, Stratix® 10 SX FPGA, Stratix® 10 TX FPGA, Stratix® III FPGA, Stratix® IV E FPGA, Stratix® IV GT FPGA, Stratix® IV GX FPGA, Stratix® V E FPGA, Stratix® V GS FPGA, Stratix® V GX FPGA |
|---|---|
| Offering Status | Production |
| Integrated Testbench | Yes |
| Evaluation License | Yes |
| Latest Quartus Version Supported | 24.3.1 |
| Development Language | Encrypted Verilog, Verilog |
Solid documentation, including User Manual and Release Note
Simulation Environment, including Simple Testbed, Test case and Test Script
Programming Register Specification
Timing Constraints in Synopsys SDC format
Access to support system and direct support from Comcores Engineers
Synopsys SGDC Files (optional)
Synopsys Lint, CDC and Waivers (optional)
Ordering Information
CM_ETHSWI_05_B_F
from Direct
Market Segment and Sub-Segments
Aerospace
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Data Center OEM (IHV, ISV, SI, VAR)
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