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The Creonic Doppler Channel IP is a Doppler shift frequency (DSF) generator capable of introducing a shift frequency to samples as a phase offset. The IP was developed to allow the performance evaluation of a low-earth orbit (LEO) digital communication system. Unlike a software-based DSF generator, which might take several hours and even days to accomplish the stated purpose, a hardware-based DSF generator requires significantly less time. Runtime is reduced by several orders of magnitude.
Creonic GmbH
Key Features
- Support for orbital heights (h) in the range from 200 to 2000 km
- Support for carrier frequencies (fc) in the range from 137 to 2200 MHz
- Support for sample frequencies (fs) in the range from 500 Ksps to 500 Gsps
- Support variations in the initial elevation angle due to different latitudes, obstructions in the visibility region, and regulatory requirements
Offering Brief
Offering Brief
| Device Family | Agilex® 3 FPGA C-Series, Agilex® 5 FPGA D-Series, Agilex® 5 FPGA E-Series, Agilex® 7 FPGA F-Series, Agilex® 7 FPGA I-Series, Agilex® 7 FPGA M-Series, Agilex® 9 FPGA Direct RF-Series, Arria® 10 GT FPGA, Arria® 10 GX FPGA, Arria® 10 SX FPGA, Arria® V GT FPGA, Arria® V GX FPGA, Arria® V GZ FPGA, Arria® V ST FPGA, Arria® V SX FPGA, Cyclone® 10 GX FPGA, Cyclone® 10 LP FPGA, Cyclone® V E FPGA, Cyclone® V GT FPGA, Cyclone® V GX FPGA, MAX® 10 FPGA, MAX® V CPLD, Stratix® 10 AX FPGA, Stratix® 10 DX FPGA, Stratix® 10 GX FPGA, Stratix® 10 SX FPGA, Stratix® 10 TX FPGA, Stratix® III FPGA, Stratix® IV E FPGA, Stratix® IV GX FPGA, Stratix® V GS FPGA, Stratix® V GX FPGA |
|---|---|
| Offering Status | Production |
| Integrated Testbench | Yes |
| Latest Quartus Version Supported | 22.4.0 |
| Development Language | C/C++, Verilog, VHDL |
Deliverable includes Verilog source code or synthesized netlist, VHDL testbench, and bit-accurate Matlab, C or C++ simulation model
Ordering Information
Creonic Doppler Channel
from Direct
