The DVB-GSE encapsulator and decapsulator IP cores close the gap between network protocols like Ethernet and the physical layer of the DVB family of standards. The DVB-GSE encapsulator performs the encapsulation of the network layer packets, also referred to as Protocol Data Units (PDUs), into one or more GSE packets, adding control information and performing integrity checks when necessary. The Creonic DVB-GSE decapsulator performs the decapsulation of BBFRAMEs, containing one or more GSE packets.
Creonic GmbH
Key Features
- Compliant with ETSI TS 102 606-1 V1.2.1 (Annex D, DVB-GSE Lite)
- Support for multi-protocol encapsulation (IPv4, IPv6, MPEG, Ethernet, etc.)
- Fragmentation of IP datagrams or other network layer packets over baseband frames (BBFRAMEs) to support ACM
- Support for single stream systems
- Support for VLSNR mode in Narrowband
- Support for 3-byte and 6-byte Labeling and Packet Filtering
- Support for Jumbo Frames
Offering Brief
Offering Brief
| Device Family | Agilex® 3 FPGA C-Series, Agilex® 5 FPGA D-Series, Agilex® 5 FPGA E-Series, Agilex® 7 FPGA F-Series, Agilex® 7 FPGA I-Series, Agilex® 7 FPGA M-Series, Agilex® 9 FPGA Direct RF-Series, Arria® 10 GT FPGA, Arria® 10 GX FPGA, Arria® 10 SX FPGA, Arria® V GT FPGA, Arria® V GX FPGA, Arria® V GZ FPGA, Arria® V ST FPGA, Arria® V SX FPGA, Cyclone® 10 GX FPGA, Cyclone® 10 LP FPGA, Cyclone® V E FPGA, Cyclone® V GT FPGA, Cyclone® V GX FPGA, MAX® 10 FPGA, MAX® V CPLD, Stratix® 10 AX FPGA, Stratix® 10 DX FPGA, Stratix® 10 GX FPGA, Stratix® 10 SX FPGA, Stratix® 10 TX FPGA, Stratix® III FPGA, Stratix® IV E FPGA, Stratix® IV GX FPGA, Stratix® V GS FPGA, Stratix® V GX FPGA |
|---|---|
| Offering Status | Production |
| Integrated Testbench | Yes |
| Latest Quartus Version Supported | 22.4.0 |
| Development Language | C/C++, Verilog, VHDL |
Deliverable includes Verilog source code or synthesized netlist, VHDL testbench, and bit-accurate Matlab, C or C++ simulation model
Ordering Information
Creonic DVB-GSE Encapsulator and Decapsulator
from Direct