Creonic IEEE 802.15.3c LDPC Decoder

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The Creonic IEEE 802.15.3c LDPC Decoder IP supports all LDPC codes with a codeword size of 672 bits as defined by the standard.

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Key Features

Compliant with IEEE 802.15.3c-2009 standard
Suitable for single carrier (SC) mode and high speed interface (HSI) mode
Support for all short LDPC codes (672 bits, code rates 1/2, 5/8, 3/4, 7/8)

Offering Brief

Device Family	Agilex® 3 FPGA C-Series, Agilex® 5 FPGA D-Series, Agilex® 5 FPGA E-Series, Agilex® 7 FPGA F-Series, Agilex® 7 FPGA I-Series, Agilex® 7 FPGA M-Series, Agilex® 9 FPGA Direct RF-Series, Arria® 10 GT FPGA, Arria® 10 GX FPGA, Arria® 10 SX FPGA, Arria® V GT FPGA, Arria® V GX FPGA, Arria® V GZ FPGA, Arria® V ST FPGA, Arria® V SX FPGA, Cyclone® 10 GX FPGA, Cyclone® 10 LP FPGA, Cyclone® V E FPGA, Cyclone® V GT FPGA, Cyclone® V GX FPGA, MAX® 10 FPGA, MAX® V CPLD, Stratix® 10 AX FPGA, Stratix® 10 DX FPGA, Stratix® 10 GX FPGA, Stratix® 10 SX FPGA, Stratix® 10 TX FPGA, Stratix® III FPGA, Stratix® IV E FPGA, Stratix® IV GX FPGA, Stratix® V GS FPGA, Stratix® V GX FPGA
Offering Status	Production
Integrated Testbench	Yes
Latest Quartus Version Supported	22.4.0
Development Language	C/C++, Verilog, VHDL

Deliverable includes Verilog source code or synthesized netlist, VHDL testbench, and bit-accurate Matlab, C or C++ simulation model

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