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The Creonic DVB-S2 LDPC / BCH Decoder and Encoder IP cores perform forward error correction as defined within the standard. Furthermore, the Encoder includes additional signal processing before and after encoding, i.e., interleaving and scrambling. The Decoder includes additional signal processing before and after forward error correction (soft-decision demapping, deinterleaving, descrambling).
Creonic GmbH
Key Features
- Compliant with ETSI EN 302 307 V1.2.1 (2009-08) (DVB-S2)
- Supports ACM, CCM, and VCM modes
- Support for decoding of BBFrames
- Support for short and long blocks (16,200 bits and 64,800 bits)
- Support for all modulation schemes (QPSK, 8-PSK, 16-APSK, and 32-APSK)
- Support for all interleaving schemes of all modulation schemes
- Support for all LDPC and BCH codes as defined by the standard
Offering Brief
Offering Brief
| Device Family | Agilex® 3 FPGA C-Series, Agilex® 5 FPGA D-Series, Agilex® 5 FPGA E-Series, Agilex® 7 FPGA F-Series, Agilex® 7 FPGA I-Series, Agilex® 7 FPGA M-Series, Agilex® 9 FPGA Direct RF-Series, Arria® 10 GT FPGA, Arria® 10 GX FPGA, Arria® 10 SX FPGA, Arria® V GT FPGA, Arria® V GX FPGA, Arria® V GZ FPGA, Arria® V ST FPGA, Arria® V SX FPGA, Cyclone® 10 GX FPGA, Cyclone® 10 LP FPGA, Cyclone® V E FPGA, Cyclone® V GT FPGA, Cyclone® V GX FPGA, MAX® 10 FPGA, MAX® V CPLD, Stratix® 10 AX FPGA, Stratix® 10 DX FPGA, Stratix® 10 GX FPGA, Stratix® 10 SX FPGA, Stratix® 10 TX FPGA, Stratix® III FPGA, Stratix® IV E FPGA, Stratix® IV GX FPGA, Stratix® V GS FPGA, Stratix® V GX FPGA |
|---|---|
| Offering Status | Production |
| Integrated Testbench | Yes |
| Latest Quartus Version Supported | 22.4.0 |
| Development Language | C/C++, Verilog, VHDL |
Deliverable includes Verilog source code or synthesized netlist, VHDL testbench, and bit-accurate Matlab, C or C++ simulation model
Ordering Information
Creonic DVB-S2 LDPC / BCH Decoder and Encoder
from Direct
