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The Creonic CCSDS LDPC IP cores support the LDPC coding scheme as defined by the CCSDS standard. The LDPC code with single rate 223/255 was specifically designed for Near-Earth missions, but the excellent error correction performance also makes it an ideal solution for a wide variety of high-throughput applications.
Creonic GmbH
Key Features
- Support for code rate 223/255 (7136/8160)
- Coded block size 8160 bits
- Compliant with “TM Synchronization and Channel Coding, Recommended Standard, CCSDS 131.0 B-3, Blue Book, September 2017”
Offering Brief
Offering Brief
| Device Family | Agilex® 3 FPGA C-Series, Agilex® 5 FPGA D-Series, Agilex® 5 FPGA E-Series, Agilex® 7 FPGA F-Series, Agilex® 7 FPGA I-Series, Agilex® 7 FPGA M-Series, Agilex® 9 FPGA Direct RF-Series, Arria® 10 GT FPGA, Arria® 10 GX FPGA, Arria® 10 SX FPGA, Arria® V GT FPGA, Arria® V GX FPGA, Arria® V GZ FPGA, Arria® V ST FPGA, Arria® V SX FPGA, Cyclone® 10 GX FPGA, Cyclone® 10 LP FPGA, Cyclone® V E FPGA, Cyclone® V GT FPGA, Cyclone® V GX FPGA, MAX® 10 FPGA, MAX® V CPLD, Stratix® 10 AX FPGA, Stratix® 10 DX FPGA, Stratix® 10 GX FPGA, Stratix® 10 SX FPGA, Stratix® 10 TX FPGA, Stratix® III FPGA, Stratix® IV E FPGA, Stratix® IV GX FPGA, Stratix® V GS FPGA, Stratix® V GX FPGA |
|---|---|
| Offering Status | Production |
| Integrated Testbench | Yes |
| Latest Quartus Version Supported | 22.4.0 |
| Development Language | C/C++, Verilog, VHDL |
Deliverable includes Verilog source code or synthesized netlist, VHDL testbench, and bit-accurate Matlab, C or C++ simulation model
Ordering Information
Creonic CCSDS LDPC Encoder and Decoder
from Direct
