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Design Gateway’s TOE25G-IP is a fully hardware-based TCP Offload Engine designed for Altera FPGAs, enabling high-throughput communication over 25Gb Ethernet. By offloading the TCP/IP stack entirely to hardware, this IP core eliminates the need for CPU intervention, reducing latency, improving determinism, and enhancing system reliability—making it ideal for high-performance computing systems, high-speed data acquisition, and mission-critical networking. The TOE25G-IP supports key TCP functions such as connection establishment, termination, retransmission, and flow control, all handled automatically in logic. With a user-friendly interface—128-bit FIFO for data transfer and register-based control—the IP simplifies integration into a wide range of systems. It supports connection establishment/termination in both client and server modes, and reference designs are available for Altera Agilex® and Stratix® 10 FPGA platforms, accelerating development and deployment ...
DesignGateway Co., Ltd.
Design Gateway’s TOE25G-IP is a fully hardware-based TCP Offload Engine designed for Altera FPGAs, enabling high-throughput communication over 25Gb Ethernet. By offloading the TCP/IP stack entirely to hardware, this IP core eliminates the need for CPU intervention, reducing latency, improving determinism, and enhancing system reliability—making it ideal for high-performance computing systems, high-speed data acquisition, and mission-critical networking. The TOE25G-IP supports key TCP functions such as connection establishment, termination, retransmission, and flow control, all handled automatically in logic. With a user-friendly interface—128-bit FIFO for data transfer and register-based control—the IP simplifies integration into a wide range of systems. It supports connection establishment/termination in both client and server modes, and reference designs are available for Altera Agilex® and Stratix® 10 FPGA platforms, accelerating development and deployment for time-sensitive applications.
Key Features
- All pure hardware TCP/IP protocol stack
- Support IPv4 protocol
- Supports Full Duplex communication
- Support both Server and Client mode (Passive/Active open and close)
- Support Jumbo frame
- 128-bit FIFO interface for data transfer
Offering Brief
Offering Brief
| Device Family | Agilex® 7 FPGA F-Series, Agilex® 7 FPGA I-Series, Stratix® 10 GX FPGA |
|---|---|
| Offering Status | Production |
| Design Examples Available | Yes |
| Demo | Yes |
| Latest Quartus Version Supported | 23.1.0 |
| Development Language | Encrypted VHDL |
Encrypted IP core
Reference Designs Quartus Project
Ordering Information
NET-T25G-IP-A7F
from Direct
NET-T25G-IP-A7F
from Macnica
NET-T25G-IP-A7F
from Uniquest
Documentation & Resources
Market Segment and Sub-Segments
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Aerospace
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Consumer
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Defense
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Government
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Medical
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Imaging
Lab/Life Sciences
Non-Imaging Patient Devices
Other Medical
Ultrasound
Video
Test
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Transportation
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Automotive (Passenger Vehicles)
Non-Automotive Transportation
Transportation Infrastructure (non-charging)