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Design Gateway’s TOE40G-IP is a high-performance, fully hardware-based TCP Offload Engine (TOE) designed for Altera FPGAs operating over 40 Gigabit Ethernet. This IP core provides high-throughput network communication by offloading the entire TCP/IP stack to the FPGA fabric. This approach reduces CPU workload, enhances system performance, and ensures deterministic behavior for mission-critical applications such as radar systems, scientific research, and industrial automation. The TOE40G-IP delivers comprehensive TCP functionality, including connection setup, termination, retransmission control, and flow management, all handled entirely in hardware. With a flexible, high-throughput 256-bit FIFO interface for data transfer and a register-based control interface, it simplifies integration into diverse system designs. The core is optimized for Arria® 10 GX FPGA platforms, and developers benefit from available reference designs and evaluation files to streamline de...
DesignGateway Co., Ltd.
Design Gateway’s TOE40G-IP is a high-performance, fully hardware-based TCP Offload Engine (TOE) designed for Altera FPGAs operating over 40 Gigabit Ethernet. This IP core provides high-throughput network communication by offloading the entire TCP/IP stack to the FPGA fabric. This approach reduces CPU workload, enhances system performance, and ensures deterministic behavior for mission-critical applications such as radar systems, scientific research, and industrial automation. The TOE40G-IP delivers comprehensive TCP functionality, including connection setup, termination, retransmission control, and flow management, all handled entirely in hardware. With a flexible, high-throughput 256-bit FIFO interface for data transfer and a register-based control interface, it simplifies integration into diverse system designs. The core is optimized for Arria® 10 GX FPGA platforms, and developers benefit from available reference designs and evaluation files to streamline development and deployment of high-speed, reliable network solutions.
Key Features
- No CPU dependency, high throughput: Delivers high-performance by offloading the entire TCP/IP stack to the FPGA, eliminating the need for external processors and ensuring efficient performance for demanding applications.
- Comprehensive TCP functionality: Includes connection setup, termination, retransmission control, and flow management—all autonomously handled in hardware for seamless operation.
- Optimized for Arria® 10 GX FPGAs: Specifically designed to work with Altera's Arria® 10 GX FPGA platforms, offering reliable performance for mission-critical applications like radar and industrial automation.
- Simplified integration: Features a register-based control interface and 256-bit FIFO data interface for ease of integration, helping developers quickly deploy the solution with minimal configuration effort.
- Available reference designs: Includes reference designs and evaluation files, enabling faster development and deployment of reliable, high-speed networking solutions.
Offering Brief
Offering Brief
| Device Family | Arria® 10 GX FPGA |
|---|---|
| Offering Status | Production |
| Design Examples Available | Yes |
| Demo | Yes |
| Hardware Platforms Supported | Arria® 10 GX FPGA Development Kit |
| Latest Quartus Version Supported | 23.1.0 |
| Development Language | Encrypted VHDL |
Encrypted IP core
Reference Designs Quartus Project
Ordering Information
NET-T40G-IP-A10
from Direct
NET-T40G-IP-A10
from Macnica
NET-T40G-IP-A10
from Uniquest
Documentation & Resources
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