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Design Gateway’s UDP-IP core series offers a fully hardware-based UDP/IP stack, eliminating the need for external CPUs. This pure hardware logic design ensures high throughput, making it ideal for systems where real-time responsiveness and consistent performance are critical. Key features of the UDP-IP core series include customizable buffer sizes, user-friendly interfaces (FIFO for data and register-based for control), and support for multicast and broadcast transmissions. Comprehensive reference designs and evaluation files are available for Altera FPGA platforms, facilitating rapid development and deployment. With a proven track record in mission-critical fields such as aerospace, defense, and high-frequency trading, Design Gateway's UDP-IP cores deliver reliable and scalable performance for high-speed network communication. By offloading the entire UDP/IP stack to hardware, they minimize CPU workload and ensure stable operation even under demanding co...
DesignGateway Co., Ltd.
Design Gateway’s UDP-IP core series offers a fully hardware-based UDP/IP stack, eliminating the need for external CPUs. This pure hardware logic design ensures high throughput, making it ideal for systems where real-time responsiveness and consistent performance are critical. Key features of the UDP-IP core series include customizable buffer sizes, user-friendly interfaces (FIFO for data and register-based for control), and support for multicast and broadcast transmissions. Comprehensive reference designs and evaluation files are available for Altera FPGA platforms, facilitating rapid development and deployment. With a proven track record in mission-critical fields such as aerospace, defense, and high-frequency trading, Design Gateway's UDP-IP cores deliver reliable and scalable performance for high-speed network communication. By offloading the entire UDP/IP stack to hardware, they minimize CPU workload and ensure stable operation even under demanding conditions.
Key Features
- Pure hardware-based UDP/IP stack with IPv4 and IP fragmentation support
- Configurable buffer sizes and 128-bit FIFO interface for high-throughput data transfer
- Full-duplex communication and multi-session support using multiple UDP25G IPs
- Multicast/broadcast Tx feature customization
- Reference designs available for Altera FPGA evaluation kits
Offering Brief
Offering Brief
| Device Family | Agilex® 7 FPGA F-Series, Agilex® 7 FPGA I-Series |
|---|---|
| Offering Status | Production |
| Design Examples Available | Yes |
| Demo | Yes |
| Latest Quartus Version Supported | 24.1.0 |
| Development Language | Encrypted VHDL |
Encrypted IP core
Reference Designs Quartus Project
Ordering Information
NET-U25G-IP
from Direct
NET-U25G-IP
from Macnica
NET-U25G-IP
from Uniquest
Documentation & Resources
Market Segment and Sub-Segments
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Aerospace
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Broadcast
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Consumer
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Defense
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Government
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Medical
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Imaging
Lab/Life Sciences
Non-Imaging Patient Devices
Other Medical
Ultrasound
Video
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Transportation
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Automotive (Passenger Vehicles)
Non-Automotive Transportation
Transportation Infrastructure (non-charging)