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Design Gateway’s UDP-IP core series offers a fully hardware-based UDP/IP stack that eliminates the need for external CPUs. This architecture ensures real-time data communication with consistent performance, making it well-suited for systems where software-based stacks fall short, such as broadcast, online gaming, industrial automation, and aerospace & defense. Key features of the UDP-IP core series include customizable buffer sizes, user-friendly interfaces (FIFO for data and register-based for control), and support for multicast and broadcast transmissions. Comprehensive reference designs and evaluation files are available for Altera FPGA platforms, enabling fast and efficient system integration. Proven in mission-critical deployments, Design Gateway's UDP-IP cores deliver a scalable and dependable solution for high-speed networking. By offloading the UDP/IP stack entirely to hardware, they help reduce CPU workload, minimize latency, and enhance syst...
DesignGateway Co., Ltd.
Design Gateway’s UDP-IP core series offers a fully hardware-based UDP/IP stack that eliminates the need for external CPUs. This architecture ensures real-time data communication with consistent performance, making it well-suited for systems where software-based stacks fall short, such as broadcast, online gaming, industrial automation, and aerospace & defense. Key features of the UDP-IP core series include customizable buffer sizes, user-friendly interfaces (FIFO for data and register-based for control), and support for multicast and broadcast transmissions. Comprehensive reference designs and evaluation files are available for Altera FPGA platforms, enabling fast and efficient system integration. Proven in mission-critical deployments, Design Gateway's UDP-IP cores deliver a scalable and dependable solution for high-speed networking. By offloading the UDP/IP stack entirely to hardware, they help reduce CPU workload, minimize latency, and enhance system reliability across a wide range of demanding applications.
Key Features
- Pure hardware-based UDP/IP stack with IPv4 and IP fragmentation support
- Configurable buffer sizes and 256-bit FIFO interface for high-throughput data transfer
- Full-duplex communication and multi-session support using multiple UDP40G IPs
- Multicast/broadcast Tx feature customization
- Reference designs available for Altera FPGA evaluation kits
Offering Brief
Offering Brief
| Device Family | Arria® 10 GX FPGA |
|---|---|
| Offering Status | Production |
| Design Examples Available | Yes |
| Demo | Yes |
| Hardware Platforms Supported | Arria® 10 GX FPGA Development Kit |
| Latest Quartus Version Supported | 23.1.0 |
| Development Language | Encrypted VHDL |
Encrypted IP core
Reference Designs Quartus Project
Ordering Information
NET-U40G-IP-A10
from Direct
NET-U40G-IP-A10
from Macnica
NET-U40G-IP-A10
from Uniquest
Documentation & Resources
Market Segment and Sub-Segments
Access
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Aerospace
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Broadcast
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Consumer
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Defense
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Government
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Medical
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Imaging
Lab/Life Sciences
Non-Imaging Patient Devices
Other Medical
Ultrasound
Video
Test
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Transportation
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Automotive (Passenger Vehicles)
Non-Automotive Transportation
Transportation Infrastructure (non-charging)