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Design Gateway’s AES-256 XTS IP core is a high-performance, hardware-only encryption engine designed for secure data protection in storage applications. The IP implements the AES algorithm in XTS (XEX-based Tweaked-codeBook mode with ciphertext Stealing) mode, which is widely used for disk encryption standards, including for SSDs and secure storage devices. Operating without the need for a CPU or software, the IP core provides real-time encryption and decryption with minimal latency, making it ideal for security-critical systems. Optimized for Altera FPGA platforms, the AES-256 XTS IP core supports 256-bit key sizes and delivers reliable and efficient encryption throughput that scales with your system’s clock and data interface configuration. It is an excellent choice for applications in defense, medical imaging, financial systems, and any domain requiring secure, high-speed data storage. Easy integration with existing Design Gateway IP cores, such as NVMe-IP ...
DesignGateway Co., Ltd.
Design Gateway’s AES-256 XTS IP core is a high-performance, hardware-only encryption engine designed for secure data protection in storage applications. The IP implements the AES algorithm in XTS (XEX-based Tweaked-codeBook mode with ciphertext Stealing) mode, which is widely used for disk encryption standards, including for SSDs and secure storage devices. Operating without the need for a CPU or software, the IP core provides real-time encryption and decryption with minimal latency, making it ideal for security-critical systems. Optimized for Altera FPGA platforms, the AES-256 XTS IP core supports 256-bit key sizes and delivers reliable and efficient encryption throughput that scales with your system’s clock and data interface configuration. It is an excellent choice for applications in defense, medical imaging, financial systems, and any domain requiring secure, high-speed data storage. Easy integration with existing Design Gateway IP cores, such as NVMe-IP or SATA-IP.
Key Features
- Support AES-XTS mode
- Support 256-bit key size
- Support input data width128-bit
- Support Ciphertext Stealing
- Peak throughput rate at 128 Mbits/MHz
- High-throughput, up to 44.8 Gbps @350MHz
Offering Brief
Offering Brief
| Device Family | Agilex® 7 FPGA F-Series, Arria® 10 SX FPGA, Stratix® 10 GX FPGA |
|---|---|
| Offering Status | Production |
| Design Examples Available | Yes |
| Demo | Yes |
| Latest Quartus Version Supported | 23.1.0 |
| Development Language | Encrypted VHDL |
Encrypted IP core
Reference Designs Quartus Project
Ordering Information
NET-AES256-XTS-IP
from Direct
NET-AES256-XTS-IP
from Macnica
NET-AES256-XTS-IP
from Uniquest
Documentation & Resources
Market Segment and Sub-Segments
Aerospace
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Consumer
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Data Center Cloud (Public, Private, Hybrid)
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Defense
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Government
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Medical
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Imaging
Lab/Life Sciences
Non-Imaging Patient Devices
Other Medical
Ultrasound
Video
Test
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Transportation
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Automotive (Passenger Vehicles)
Non-Automotive Transportation
Transportation Infrastructure (non-charging)