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Secure communication with cryptographic algorithms requires intensive computation power and massively CPU time consuming to complete the tasks. Real-time secure communication processing while fully utilizing network bandwidth over 25G, 100G or more is very important, especially, in modern day Data Center. AES-GCM is recommended symmetric-key cryptographic block ciphers for trusted protocols such as TLS and SSL, approved by NIST. By implementing AES256-GCM-100G IP core on FPGA as Hardware Acceleration, TLS and SSL communication can be processed in real-time at 100G Ethernet speed. Design Gateway's AES256-GCM100G IP Core is designed to meet NIST standards with high performance throughput over 100Gbps. It's suitable TLS and SSL offload and acceleration by FPGA for any application that required 100G throughput over secure network communication.
DesignGateway Co., Ltd.
Key Features
- Support AES-GCM mode standard
- Support 256-bit key size, 96-bit iv size
- Support zero-length AAD or data input
- Peak throughput rate at 512 Mbits/MHz
- High-throughput, up to 138.24 Gbps @270MHz
- NIST SP 800-38D Compliance
Offering Brief
Offering Brief
| Device Family | Agilex® 7 FPGA F-Series, Arria® 10 SX FPGA |
|---|---|
| Offering Status | Production |
| Design Examples Available | Yes |
| Demo | Yes |
| Latest Quartus Version Supported | 23.1.0 |
| Development Language | Encrypted VHDL |
Encrypted IP core
Reference Designs Quartus Project
Ordering Information
NET-AES256-GCM-100G-IP
from Direct
NET-AES256-GCM-100G-IP
from Macnica
NET-AES256-GCM-100G-IP
from Uniquest
Market Segment and Sub-Segments
Aerospace
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Consumer
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Data Center Cloud (Public, Private, Hybrid)
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Imaging
Lab/Life Sciences
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Transportation
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