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Secure communication with cryptographic algorithms requires intensive computation power and massively CPU time consuming to complete the tasks. Real-time secure communication processing while fully utilizing network bandwidth over 25G is very important, especially, in modern day Data Center. AES-GCM is recommended symmetric-key cryptographic block ciphers for trusted protocols such as TLS and SSL, approved by NIST. By implementing AES256-GCM-10G25G IP core on FPGA as Hardware Acceleration, TLS and SSL communication can be processed in real-time at 10G/25G Ethernet speed. Design Gateway's AES256-GCM10G25G IP Core is designed to meet NIST standards with high performance throughput over 10/25Gbps. It's suitable TLS and SSL offload and acceleration by FPGA for any application that required 10G/25G throughput over secure network communication.
DesignGateway Co., Ltd.
Key Features
- Support AES-GCM mode standard.
- Support 128/256-bit key size, 96-bit iv size.
- Support zero-length AAD or data input.
- Peak throughput rate at 128 Mbits/MHz
- High-throughput, up to 38.4 Gbps @300MHz
- NIST SP 800-38D Compliance
Offering Brief
Offering Brief
| Device Family | Agilex® 7 FPGA F-Series, Arria® 10 SX FPGA |
|---|---|
| Offering Status | Production |
| Design Examples Available | Yes |
| Demo | Yes |
| Latest Quartus Version Supported | 23.1.0 |
| Development Language | Encrypted VHDL |
Encrypted IP core
Reference Designs Quartus Project
Ordering Information
NET-AES256-GCM-10G25G-IP
from Direct
NET-AES256-GCM-10G25G-IP
from Macnica
NET-AES256-GCM-10G25G-IP
from Uniquest
Market Segment and Sub-Segments
Aerospace
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Consumer
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Data Center Cloud (Public, Private, Hybrid)
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Defense
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Government
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Medical
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Imaging
Lab/Life Sciences
Non-Imaging Patient Devices
Other Medical
Ultrasound
Video
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Test
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Transportation
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Automotive (Passenger Vehicles)
Non-Automotive Transportation
Transportation Infrastructure (non-charging)