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AES-128 IP supports ECB mode for both encryption and decryption, processing 128-bit data blocks in a constant 11 clock cycles. It delivers 11.6 Mbps per MHz, achieving up to 4.65 Gbps at 400 MHz. Designed to enhance the security of data storage and networking IP cores, it enables secure, efficient, and high-performance applications.
DesignGateway Co., Ltd.
Key Features
- Support AES ECB mode standard.
- Support 128-bit key size.
- Support input data width128-bit.
- Throughput rate at 11.6 Mbits/MHz.
- Speed up to 4.65 Gbps @400MHz.
- 128-bit data calculation time is constant at 11 clock cycles.
Offering Brief
Offering Brief
| Device Family | Agilex® 7 FPGA F-Series, Arria® 10 SX FPGA |
|---|---|
| Offering Status | Production |
| Design Examples Available | Yes |
| Demo | Yes |
| Latest Quartus Version Supported | 23.1.0 |
| Development Language | Encrypted VHDL |
Encrypted IP core
Reference Designs Quartus Project
Ordering Information
NET-AES128-IP
from Direct
NET-AES128-IP
from Macnica
Documentation & Resources
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