.webp){kind=small}
SHA-256 IP is an optimized and efficient implementation of the SHA-256 algorithm, compliant with the FIPS 180-4 standard. It processes 512-bit data blocks in 65 clock cycles, delivering 7.875 Mbps per MHz—equivalent to 1.575 Gbps at 200 MHz. When combined with Design Gateway's data storage and networking IPs, it enables the development of secure, high-performance, and efficient applications.
DesignGateway Co., Ltd.
Key Features
- Support SHA 256-bit standard function
- Support input data length up to 2^61-1 bytes (2^64-8 bits)
- Super high throughtput rate at 65 clocks per 64 bytes data (1.015625 cycles/byte).
- Hash speed up to 1.575 Gbps @ 200MHz.
- Simple user interface signals as same as FIFO interface.
Offering Brief
Offering Brief
| Device Family | Arria® 10 SX FPGA |
|---|---|
| Offering Status | Production |
| Design Examples Available | Yes |
| Demo | Yes |
| Hardware Platforms Supported | Arria® 10 SX SoC Development Kit |
| Latest Quartus Version Supported | 23.1.0 |
| Development Language | Encrypted VHDL |
Encrypted IP core
Reference Designs Quartus Project
Ordering Information
NET-SHA256-IP
from Direct
NET-SHA256-IP
from Macnica
NET-SHA256-IP
from Uniquest
Documentation & Resources
Market Segment and Sub-Segments
Aerospace
View Sub-Segments
Consumer
View Sub-Segments.svg?h=0&v=8a74a614-b7ba-4604-ad78-f0827c6a3874&itok=rVWXlOCO)
Defense
View Sub-Segments
Government
View Sub-Segments
Medical
View Sub-SegmentsMedical
Imaging
Lab/Life Sciences
Non-Imaging Patient Devices
Other Medical
Ultrasound
Video
Image
Test
View Sub-Segments
Transportation
View Sub-SegmentsTransportation
Automotive (Passenger Vehicles)
Non-Automotive Transportation
Transportation Infrastructure (non-charging)