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DCAN FD - Configurable CAN Bus Controller with Flexible Data-Rate

DCD-SEMI

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Introducing DCD’s Ingenious DCAN FD IP Core: Empowering Engineers with Unparalleled Flexibility.

When it comes to seamlessly infusing cutting-edge Controller Area Network (CAN) capabilities into diverse systems, look no further than DCD’s DCAN FD IP Core. This engineering marvel can be harnessed as a standalone powerhouse, an integral part of an ASIC, or an FPGA marvel. Guided by the ISO11898-1:2015 standard, it ushers in flawless communication aligned with industry-favorite protocols, making it a game-changer for engineers and innovators.

Engineered to cater to both Classical CAN and the dynamic CAN FD, this module does require external transceiver hardware to establish a tangible link to the CAN bus. Our ingenious approach employs a single or dual-ported Message RAM, strategically situated outside the module, connected through the versatile Generic Master Interface. This meticulous design simplifies the art of message handling, ensuring efficiency at every turn.

Introducing DCD’s Ingenious DCAN FD IP Core: Empowering Engineers with Unparalleled Flexibility.

When it comes to seamlessly infusing cutting-edge Controller Area Network (CAN) capabilities into diverse systems, look no further than DCD’s DCAN FD IP Core. This engineering marvel can be harnessed as a standalone powerhouse, an integral part of an ASIC, or an FPGA marvel. Guided by the ISO11898-1:2015 standard, it ushers in flawless communication aligned with industry-favorite protocols, making it a game-changer for engineers and innovators.

Engineered to cater to both Classical CAN and the dynamic CAN FD, this module does require external transceiver hardware to establish a tangible link to the CAN bus. Our ingenious approach employs a single or dual-ported Message RAM, strategically situated outside the module, connected through the versatile Generic Master Interface. This meticulous design simplifies the art of message handling, ensuring efficiency at every turn.

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Key Features

  • Developed as ISO26262-10 Safety Element out of Context
  • Designed in accordance to ISO 11898-1:2015 specification
  • Supports CAN and CAN FD frames
  • Supports up to 64 bytes data frame
  • Flexible data rates supported
  • Data rate up to 8Mbps
  • Up to 32 configured Acceptance Filters - Hardware message filtering (dual/single filters)
  • DMA support for transmit and receive
  • 3 TX buffers
  • Configurable RX FIFO size
  • Overload frame is generated on FIFO overflow
  • Protocol Exception Event detection
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Offering Brief

Offering Brief

Device Family Agilex® 3 FPGA C-Series, Agilex® 5 FPGA D-Series, Agilex® 5 FPGA E-Series, Agilex® 7 FPGA F-Series, Agilex® 7 FPGA I-Series, Agilex® 7 FPGA M-Series, Agilex® 9 FPGA Direct RF-Series, Arria® 10 GT FPGA, Arria® 10 GX FPGA, Arria® 10 SX FPGA, Arria® V GT FPGA, Arria® V GX FPGA, Arria® V GZ FPGA, Arria® V ST FPGA, Arria® V SX FPGA, Cyclone® 10 GX FPGA, Cyclone® 10 LP FPGA, Cyclone® III FPGA, Cyclone® IV E FPGA, Cyclone® IV GX FPGA, Cyclone® V E FPGA, Cyclone® V GT FPGA, Cyclone® V GX FPGA, Cyclone® V SE FPGA, Cyclone® V ST FPGA, Cyclone® V SX FPGA, MAX® 10 FPGA, MAX® V CPLD, Stratix® 10 AX FPGA, Stratix® 10 DX FPGA, Stratix® 10 GX FPGA, Stratix® 10 SX FPGA, Stratix® 10 TX FPGA, Stratix® III FPGA, Stratix® IV E FPGA, Stratix® IV GX FPGA, Stratix® V GS FPGA, Stratix® V GX FPGA
Offering Status Production
Integrated Testbench Yes
Evaluation License Yes
Design Examples Available Yes
Latest Quartus Version Supported 25.1.1
Development Language Encrypted Verilog, Verilog

HDL Source Code

Testbench environment - automatic simulation macros, tests with reference responses

Synthesis scripts

Technical documentation

12 months of technical support

Ordering Information

DCAN FD

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Documentation & Resources

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