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The DESPI is a fully configurable eSPI master/slave device supporting all features described in Enhanced Serial Peripheral Interface Base Specification rev. 1.0. The DESPI master is to be used by the microcontroller to communicate with eSPI peripheral devices. The DESPI slave is to be used as an eSPI peripheral device, e.g. an Embedded Controller attached to the Intel CPU system.
DCD-SEMI
Key Features
- Compliant with eSPI base specification as defined in Enhanced Serial Peripheral Interface (eSPI) Specification rev.1.0
- Supports Master and Slave Modes
- Supports Single, Dual and Quad modes
- Supports TX and RX operation as per specs
- Support for Command Phase, Turn-Around Phase, Response Phase
- Baud Rate selection
- Slave Triggered Transactions
- Power management Event
- Interrupts and Alerts
- In-band reset
- Support for multiple channels: Peripheral channel, Virtual wire Channel, OOB Message (Tunneled SMBus) Channel, Run-time Flash Access Channel
- Various Master/Slave errors detection
Offering Brief
Offering Brief
| Device Family | Agilex® 3 FPGA C-Series, Agilex® 5 FPGA D-Series, Agilex® 5 FPGA E-Series, Agilex® 7 FPGA F-Series, Agilex® 7 FPGA I-Series, Agilex® 7 FPGA M-Series, Agilex® 9 FPGA Direct RF-Series, Arria® 10 GT FPGA, Arria® 10 GX FPGA, Arria® 10 SX FPGA, Arria® V GT FPGA, Arria® V GX FPGA, Arria® V GZ FPGA, Arria® V ST FPGA, Arria® V SX FPGA, Cyclone® 10 GX FPGA, Cyclone® 10 LP FPGA, Cyclone® III FPGA, Cyclone® IV E FPGA, Cyclone® IV GX FPGA, Cyclone® V E FPGA, Cyclone® V GT FPGA, Cyclone® V GX FPGA, Cyclone® V SE FPGA, Cyclone® V ST FPGA, Cyclone® V SX FPGA, MAX® 10 FPGA, MAX® V CPLD, Stratix® 10 AX FPGA, Stratix® 10 DX FPGA, Stratix® 10 GX FPGA, Stratix® 10 SX FPGA, Stratix® 10 TX FPGA, Stratix® III FPGA, Stratix® IV E FPGA, Stratix® IV GX FPGA, Stratix® V GS FPGA, Stratix® V GX FPGA |
|---|---|
| Offering Status | Production |
| Integrated Testbench | Yes |
| Evaluation License | Yes |
| Design Examples Available | Yes |
| Latest Quartus Version Supported | 25.1.1 |
| Development Language | Encrypted Verilog, Verilog |
HDL Source Code
Testbench environment - automatic simulation macros, tests with reference responses
Synthesis scripts
Technical documentation
12 months of technical support
Ordering Information
DESPI
from Direct
Documentation & Resources
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