.webp){kind=small}
DMESCC – Dual channel Multiprotocol Enhanced Serial Communication Controller, is designed for use with 8- and 16- bit microprocessors. DMESCC handles asynchronous formats, synchronous byte-oriented protocols such as IBM® Bisync, and synchronous bit-oriented protocols such as HDLC and SDLC. The device can generate and check CRC codes in any synchronous mode and can be programmed to check data integrity in various modes. The DMESCC also has facilities for modem control in both channels.
DCD-SEMI
Key Features
- Dual-Channel: A, B
- Configuration capability
- Asynchronous mode: Asynchronous (x16, x32, or x64 clock), Isochronous (x1 clock)
- Character-Oriented mode: Monosynchronous, Bisynchronous, External Synchronous
- Bit-Oriented mode: SDLC/HDLC, SDLC/HDLC Loop
- Complete status reporting capabilities
- Receiver data FIFO and Error FIFO
- SDLC Frame FIFO
- Transmitter FIFO
- Data encoder\decoder: NRZ, NRZI, FM0, FM1, Manchester (require external logic)
- Line break generation and detection
- Internal diagnostic capabilities: Loop-back controls for communications link fault isolation, Auto Echo, Break, parity, overrun, framing error simulation
Offering Brief
Offering Brief
| Device Family | Agilex® 3 FPGA C-Series, Agilex® 5 FPGA D-Series, Agilex® 5 FPGA E-Series, Agilex® 7 FPGA F-Series, Agilex® 7 FPGA I-Series, Agilex® 7 FPGA M-Series, Agilex® 9 FPGA Direct RF-Series, Arria® 10 GT FPGA, Arria® 10 GX FPGA, Arria® 10 SX FPGA, Arria® V GT FPGA, Arria® V GX FPGA, Arria® V GZ FPGA, Arria® V ST FPGA, Arria® V SX FPGA, Cyclone® 10 GX FPGA, Cyclone® 10 LP FPGA, Cyclone® III FPGA, Cyclone® IV E FPGA, Cyclone® IV GX FPGA, Cyclone® V E FPGA, Cyclone® V GT FPGA, Cyclone® V GX FPGA, Cyclone® V SE FPGA, Cyclone® V ST FPGA, Cyclone® V SX FPGA, MAX® 10 FPGA, MAX® V CPLD, Stratix® 10 AX FPGA, Stratix® 10 DX FPGA, Stratix® 10 GX FPGA, Stratix® 10 SX FPGA, Stratix® 10 TX FPGA, Stratix® III FPGA, Stratix® IV E FPGA, Stratix® IV GX FPGA, Stratix® V GS FPGA, Stratix® V GX FPGA |
|---|---|
| Offering Status | Production |
| Integrated Testbench | Yes |
| Evaluation License | Yes |
| Design Examples Available | Yes |
| Latest Quartus Version Supported | 25.1.1 |
| Development Language | Encrypted Verilog, Encrypted VHDL, Verilog, VHDL |
HDL Source Code
Testbench environment - automatic simulation macros, tests with reference responses
Synthesis scripts
Technical documentation
12 months of technical support
Ordering Information
DMESCC
from Direct
Documentation & Resources
Market Segment and Sub-Segments
Aerospace
View Sub-Segments
ASIC Proto
View Sub-Segments
Consumer
View Sub-Segments.svg?h=0&v=8a74a614-b7ba-4604-ad78-f0827c6a3874&itok=rVWXlOCO)
Defense
View Sub-Segments
Government
View Sub-Segments
Industrial
View Sub-Segments
Medical
View Sub-SegmentsMedical
Imaging
Lab/Life Sciences
Non-Imaging Patient Devices
Other Medical
Ultrasound
Video
Transportation
View Sub-SegmentsTransportation
Automotive (Passenger Vehicles)
Charging Infrastructure
Non-Automotive Transportation
Transportation Infrastructure (non-charging)