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Soft core of a Universal Synchronous and Asynchronous Receiver/Transmitter (UART), functionally compatible to the OX16C950. Allows serial transmission in two modes: UART and FIFO. In the FIFO mode, internal FIFOs are activated allowing 128 bytes (plus 3 bits of error data per byte in the RCVR FIFO) to be stored in both receive and transmit modes. Our efficient Core performs serial-to-parallel conversion on data characters received from a peripheral device or MODEM, but also parallel-to-serial conversion on data characters received from the CPU. The processor can read the complete status of the UART at any time during the functional operation. The reported status information includes the type and condition of transfer operations performed by the UART, as well as any error conditions (parity, overrun, framing, or break interrupt). The D16950 includes a programmable baud rate generator which is able to divide a timing reference clock input by divisors of 1 to (21...
DCD-SEMI
Soft core of a Universal Synchronous and Asynchronous Receiver/Transmitter (UART), functionally compatible to the OX16C950. Allows serial transmission in two modes: UART and FIFO. In the FIFO mode, internal FIFOs are activated allowing 128 bytes (plus 3 bits of error data per byte in the RCVR FIFO) to be stored in both receive and transmit modes. Our efficient Core performs serial-to-parallel conversion on data characters received from a peripheral device or MODEM, but also parallel-to-serial conversion on data characters received from the CPU. The processor can read the complete status of the UART at any time during the functional operation. The reported status information includes the type and condition of transfer operations performed by the UART, as well as any error conditions (parity, overrun, framing, or break interrupt). The D16950 includes a programmable baud rate generator which is able to divide a timing reference clock input by divisors of 1 to (216-1) and produce an n × clock for driving internal transmitter logic. Provisions are also included to use this n × clock to drive receiver logic. We also equipped our core with complete MODEM-control capability and a processor-interrupt system. Interrupts can be programmed according to your requirements, minimizing the computing required to handle the communications link. The D16950 core includes all (16450, 16550, 16650 and 16750) features and additional functions.
Key Features
- Software compatible with 16450, 16550,16650,16750 and 16950 UARTs
- Synchronous and Asynchronous transmission
- Configuration capability
- Supports RS232 and RS485 standards
- Separate configurable BAUD clock line
- Supports IRDA data format mode
- Majority Voting Logic
- Two modes of operation: UART mode and FIFO mode - In the FIFO mode transmitter and receiver are each buffered with 128 byte FIFO to reduce the number of interrupts presented to the CPU; In UART mode receiver and transmitter are double buffered to eliminate a need for precise synchronization between the CPU and serial data
- FIFO size – 128 Bytes (Optional FIFO size extension to 256 or 512 Bytes)
- Adds or deletes standard asynchronous communication bits (start, stop and parity) to or from the serial data
- Independently controlled transmit, receive, line status and data set interrupts
- False start bit detection
Offering Brief
Offering Brief
| Device Family | Agilex® 3 FPGA C-Series, Agilex® 5 FPGA D-Series, Agilex® 5 FPGA E-Series, Agilex® 7 FPGA F-Series, Agilex® 7 FPGA I-Series, Agilex® 7 FPGA M-Series, Agilex® 9 FPGA Direct RF-Series, Arria® 10 GT FPGA, Arria® 10 GX FPGA, Arria® 10 SX FPGA, Arria® V GT FPGA, Arria® V GX FPGA, Arria® V GZ FPGA, Arria® V ST FPGA, Arria® V SX FPGA, Cyclone® 10 GX FPGA, Cyclone® 10 LP FPGA, Cyclone® III FPGA, Cyclone® IV E FPGA, Cyclone® IV GX FPGA, Cyclone® V E FPGA, Cyclone® V GT FPGA, Cyclone® V GX FPGA, Cyclone® V SE FPGA, Cyclone® V ST FPGA, Cyclone® V SX FPGA, MAX® 10 FPGA, MAX® V CPLD, Stratix® 10 AX FPGA, Stratix® 10 DX FPGA, Stratix® 10 GX FPGA, Stratix® 10 SX FPGA, Stratix® 10 TX FPGA, Stratix® III FPGA, Stratix® IV E FPGA, Stratix® IV GX FPGA, Stratix® V GS FPGA, Stratix® V GX FPGA |
|---|---|
| Offering Status | Production |
| Integrated Testbench | Yes |
| Evaluation License | Yes |
| Design Examples Available | Yes |
| Latest Quartus Version Supported | 25.1.1 |
| Development Language | Encrypted Verilog, Verilog |
HDL Source Code
Testbench environment - automatic simulation macros, tests with reference responses
Synthesis scripts
Technical documentation
12 months of technical support
Ordering Information
D16950
from Direct
Documentation & Resources
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