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The IPC-NV171A-BR-bp is architected for extreme security environments requiring a physical and logical "air-gap" within the FPGA fabric. It establishes a definitive boundary between the unencrypted "Red" domain and the encrypted "Black" domain, ensuring that sensitive data cannot bleed across the interface. This "bp" variant includes a dedicated, hardware-validated bypass path that allows critical non-sensitive management commands to pass through without traditional encryption processing. This ensures the storage device remains fully manageable by the host OS while the primary data payload remains cryptographically isolated.
IntelliProp: Experts in Memory and Data Storage IP
Key Features
- Physical Domain Separation: Strict hardware partitioning of the FPGA fabric to isolate plaintext and ciphertext.
- Validated Bypass Path: Dedicated logic for the secure passage of non-sensitive NVMe management commands.
- Zero Host Impact: Appears as a standard NVMe device; requires no custom host-side drivers.
- Full-Duplex Encryption: Supports line-rate AES-XTS (128/256-bit) across the secure partition.
- Advanced Error Isolation: Protocol errors in one domain are isolated to prevent cross-domain data leakage.
- High Availability: Supports hot-swap and advanced power management features for enterprise and military backplanes.
Offering Brief
Offering Brief
| Device Family | Agilex® 5 FPGA D-Series, Agilex® 5 FPGA E-Series, Agilex® 7 FPGA F-Series, Agilex® 7 FPGA I-Series, Agilex® 9 FPGA Direct RF-Series, Arria® 10 GT FPGA, Arria® 10 GX FPGA, Arria® 10 SX FPGA, Stratix® 10 AX FPGA, Stratix® 10 DX FPGA, Stratix® 10 GX FPGA, Stratix® 10 SX FPGA, Stratix® 10 TX FPGA |
|---|---|
| Offering Status | Production |
| Integrated Testbench | Yes |
| Evaluation License | Yes |
| Design Examples Available | Yes |
| Compliance | Yes |
| Latest Quartus Version Supported | 25.3.0 |
| Development Language | Encrypted Verilog, Encrypted VHDL, Verilog, VHDL |
Encrypted Verilog RTL with strict Red/Black domain isolation
ModelSim/Questa verification models with Bypass-path validation
Reference Design for an Altera Development Kit featuring Red/Black isolation
Synthesis and Place-and-Route scripts with pre-defined physical partitioning constraints
High-Assurance Technical Guide focusing on partitioning and bypass logic
Ordering Information
IPC-NV171A-BR-bp
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