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The IPP-NV188A-1BR is designed to sit transparently between an NVMe host and an NVMe target, providing robust hardware-level security without the latency penalties associated with software encryption. By utilizing IntelliProp's high-efficiency bridging architecture, the core performs real-time AES-XTS encryption and decryption as data passes through the FPGA. This allows for the immediate conversion of standard NVMe SSDs into self-encrypting drives (SEDs). It is ideal for secure server environments, edge computing, and military storage where data-at-rest protection is a mandatory requirement.
IntelliProp: Experts in Memory and Data Storage IP
Key Features
- Protocol Support: Transparent bridging of NVMe commands and data (PCIe Gen3/Gen4/Gen5).
- Advanced Encryption: Integrated 128/256-bit AES-XTS hardware engine.
- Transparency: No custom host-side drivers required; appears as a standard NVMe device.
- Scalability: Supports multiple NVMe namespaces and complex command sets.
- High Throughput: Designed for line-rate encryption with minimal impact on IOPS performance.
- Key Management: Secure interface for loading and managing encryption keys within the FPGA.
Offering Brief
Offering Brief
| Device Family | Agilex® 5 FPGA E-Series, Agilex® 7 FPGA F-Series, Stratix® 10 GX FPGA |
|---|---|
| Offering Status | Production |
| Integrated Testbench | Yes |
| Evaluation License | Yes |
| Design Examples Available | Yes |
| Compliance | Yes |
| Hardware Platforms Supported | Agilex® 7 FPGA Starter Kit |
| Latest Quartus Version Supported | 25.3.0 |
| Development Language | Encrypted Verilog, Encrypted VHDL, Verilog |
Encrypted Verilog RTL
ModelSim/Questa verification models and a complete encryption-focused testbench
Reference Design showing host-to-target NVMe data flow with encryption enabled
Synthesis and Place-and-Route scripts for Altera Quartus Prime Pro
Technical documentation covering key management and AES-XTS configuration
Ordering Information
IPP-NV188A-1BR
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