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The IPP-NV186A-BR provides a seamless bridge between a PCIe/NVMe host interface and a Serial-ATA (SATA) target. This core allows an Altera FPGA to appear as a standard NVMe drive to the host system while managing all the complex command translation and protocol mapping required to talk to standard SATA storage. By utilizing hardware-automated translation, it eliminates the need for complex software stacks or custom drivers, allowing for a "plug-and-play" experience when integrating legacy SATA storage into modern, NVMe-centric architectures.
IntelliProp: Experts in Memory and Data Storage IP
Key Features
- Transparency: Fully transparent to the host; utilizes native NVMe drivers.
- Protocol Mapping: Automated translation of NVMe Command Sets to SATA Task Files.
- Performance: Supports high-efficiency DMA for maximum data throughput between interfaces.
- Compliance: Fully compliant with NVMe 1.3/1.4 and SATA 3.3 specifications.
- Scalability: Supports multiple NVMe queues and deep command sets.
- Error Handling: Integrated hardware error detection and reporting for both NVMe and SATA protocol layers.
Offering Brief
Offering Brief
| Device Family | Agilex® 5 FPGA E-Series, Agilex® 7 FPGA F-Series, Arria® 10 GT FPGA, Arria® 10 GX FPGA, Arria® 10 SX FPGA, Cyclone® 10 GX FPGA |
|---|---|
| Offering Status | Production |
| Integrated Testbench | Yes |
| Evaluation License | Yes |
| Design Examples Available | Yes |
| Compliance | Yes |
| Hardware Platforms Supported | Agilex® 7 FPGA Starter Kit |
| Latest Quartus Version Supported | 25.3.0 |
| Development Language | Encrypted Verilog, Encrypted VHDL, Verilog, VHDL |
Encrypted Verilog RTL for NVMe-to-SATA translation logic
ModelSim/Questa verification models and bridge-specific testbench
Reference Design for an Altera Development Kit (PCIe to SATA)
Synthesis and Place-and-Route scripts for Altera Quartus Prime Pro
Comprehensive User Documentation and register mapping guide
Ordering Information
IPP-NV186A-B
from Direct
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