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The latest-generation CMOS image sensor interface. SLVS-EC v3.1 RX IP is an interface IP core that runs on Altera® FPGAs. By using this IP core, you can quickly and easily create products that support the latest SLVS-EC standard v3.1. An evaluation kit is also provided for early adoption.
Macnica Americas
Key Features
- The receive function from SLVS-EC interface using Altera® FPGA, Supports the latest SLVS-EC Specification Version 3.1, Powerful De-Skew function that allows you to design boards without having to worry about skew between lanes.
Offering Brief
Offering Brief
| Device Family | Agilex® 3 FPGA C-Series, Agilex® 5 FPGA D-Series, Agilex® 5 FPGA E-Series, Agilex® 7 FPGA F-Series, Agilex® 7 FPGA I-Series, Agilex® 7 FPGA M-Series, Arria® 10 GT FPGA, Arria® 10 GX FPGA, Arria® 10 SX FPGA, Arria® V GT FPGA |
|---|---|
| Offering Status | Production |
| Evaluation License | Yes |
| Design Examples Available | Yes |
| Development Language | Verilog, VHDL |
IP core image
Documentation
Market Segment and Sub-Segments
Aerospace
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Broadcast
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Consumer
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Defense
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Government
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Industrial
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