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Highly configurable Enterprise Flash Controller for ONFI 5.2 and Toggle NAND with NV-LPDDR4 mode, device-independent RTL, and software-defined command sequencing for high-throughput SSD designs. EFC provides 16–256-bit datapaths (PHY 16/32-bit), supports volume addressing, suspend/resume, two-pass programming, multi-plane & async plane-read, and can run a UI asynchronous to the flash interface. Per-device or wired-OR Ready/Busy is configurable. Up to 256 LUNs/channel with virtual LUNs to right-size gate count; independent, pipelined command/data/report interfaces allow multiple in-flight commands to different CS/LUNs. Delivered as technology-independent RTL with complete HVL/UVM testbench, docs, and FPGA prototype netlist.
Mobiveil Inc.
Key Features
- Data path widths support of 16 bits to 256 bits PHY Data path width - 16 bit , 32bit
- Supports ONFI 5.2 specification with NV-LPDDR4 mode of operation
- Device independent RTL can work with any NAND device with just software reprogramming
- Configurable Ready Busy Signal Configuration (Per device or Wired OR)
- Supports volume addressing, suspend/resume functions, two pass programming, multi plane and asynchronous plane read commands
- Supports User Interface to be Asynchronous with Flash Interface
- Supports up to 256 LUNs per channel
- Supports virtual LUNs feature to limit the gate count of EFC based on maximum possible simultaneous LUN operations in the end user system.
- Configurable warmup cycles through CSR register
- DBI support
- Support for SCA Protocol
- Transaction based user interface and Software definable address scheme
Offering Brief
Offering Brief
| Device Family | Agilex® 3 FPGA C-Series, Agilex® 5 FPGA D-Series, Agilex® 5 FPGA E-Series, Agilex® 7 FPGA F-Series, Agilex® 7 FPGA I-Series, Agilex® 7 FPGA M-Series, Agilex® 9 FPGA Direct RF-Series, Arria® 10 GT FPGA, Arria® 10 GX FPGA, Arria® 10 SX FPGA, Arria® II GX FPGA, Arria® V GT FPGA, Arria® V GX FPGA, Arria® V GZ FPGA, Arria® V ST FPGA, Arria® V SX FPGA, Cyclone® 10 GX FPGA, Cyclone® 10 LP FPGA, Cyclone® III FPGA, Cyclone® IV E FPGA, Cyclone® IV GX FPGA, Cyclone® V E FPGA, Cyclone® V GT FPGA, Cyclone® V GX FPGA, Cyclone® V SE FPGA, Cyclone® V ST FPGA, Cyclone® V SX FPGA, MAX® 10 FPGA, Stratix® 10 AX FPGA, Stratix® 10 DX FPGA, Stratix® 10 GX FPGA, Stratix® 10 SX FPGA, Stratix® 10 TX FPGA, Stratix® III FPGA, Stratix® IV E FPGA, Stratix® IV GX FPGA, Stratix® V GS FPGA, Stratix® V GX FPGA |
|---|---|
| Offering Status | Production |
| Integrated Testbench | Yes |
| Evaluation License | Yes |
| Development Language | Encrypted Verilog, Verilog |
Configurable RTL Code
HVL based test bench & Test cases
FPGA Netlist for Prototype
Synthesis Scripts
Design Guide
Verification Guide
Synthesis Guide
Documentation
Ordering Information
NA
from Direct
Documentation & Resources
Market Segment and Sub-Segments
ASIC Proto
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Consumer
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Data Center Cloud (Public, Private, Hybrid)
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Data Center OEM (IHV, ISV, SI, VAR)
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AI/HPC
CDNs
IaaS/PaaS
Networking
Storage
Transmission
Industrial
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Transportation
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Automotive (Passenger Vehicles)
Transportation Infrastructure (non-charging)
