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Configurable LDPC Encoder/Decoder IP for eMMC/flash controllers delivering high endurance and retention with industry-leading reliability, performance, and low power; scales from 50 MB/s to 9.0 GB/s per instance. Technology-independent, system-validated LDPC core tailored to eMMC/flash pipelines with soft-information (LLR) support. Each instance is optimized for codeword size, parity, parallelism, and memory access options, and targets eASIC/FPGA/ASIC (40→10 nm). Deliverables include LDPC compiler & matrix-generation source, an FPGA LLR reference design (MATLAB interface), and a UVM environment with encoder, error injector, and decoder.
Mobiveil Inc.
Key Features
- Supporting a wide range of data-rates
- 50MB/s to 9.0GB/s for a single LDPC instance
- Scalable platform provides the basis for customer specific custom-LDPC cores
- Codeword size, supports wide range of codewords
- Maximum amount of supported parity
- High degree of parallelism for high data-rate applications
- Different Memory access options
- Platform specific options (eASIC, FPGA, 40nm ASIC, 28nm ASIC, 16nm ASIC,10nm ASIC)
- Simultaneous support for different amounts of parity
- Simultaneous support for several LDPC codes
- On-the-fly switching from one LDPC code to another
- Low area and power
Offering Brief
Offering Brief
| Device Family | Agilex® 3 FPGA C-Series, Agilex® 5 FPGA D-Series, Agilex® 5 FPGA E-Series, Agilex® 7 FPGA F-Series, Agilex® 7 FPGA I-Series, Agilex® 7 FPGA M-Series, Agilex® 9 FPGA Direct RF-Series, Arria® 10 GT FPGA, Arria® 10 GX FPGA, Arria® 10 SX FPGA, Arria® II GX FPGA, Arria® V GT FPGA, Arria® V GX FPGA, Arria® V GZ FPGA, Arria® V ST FPGA, Arria® V SX FPGA, Cyclone® 10 GX FPGA, Cyclone® 10 LP FPGA, Cyclone® III FPGA, Cyclone® IV E FPGA, Cyclone® IV GX FPGA, Cyclone® V E FPGA, Cyclone® V GT FPGA, Cyclone® V GX FPGA, Cyclone® V SE FPGA, Cyclone® V ST FPGA, Cyclone® V SX FPGA, MAX® 10 FPGA, Stratix® 10 AX FPGA, Stratix® 10 DX FPGA, Stratix® 10 GX FPGA, Stratix® 10 SX FPGA, Stratix® 10 TX FPGA, Stratix® III FPGA, Stratix® IV E FPGA, Stratix® IV GX FPGA, Stratix® V GS FPGA, Stratix® V GX FPGA |
|---|---|
| Offering Status | Production |
| Integrated Testbench | Yes |
| Evaluation License | Yes |
| Latest Quartus Version Supported | 24.3.1 |
| Development Language | Encrypted Verilog, Verilog |
Source Code for LDPC Compiler
Source Code for LDPC Matrix Generation Software
FPGA based LLR generation reference design with MATLAB interface
UVM verification env with encoder, error injector and decoder instantiate
IP User Guide
Synthesis Guide
Ordering Information
NA
from Direct
Documentation & Resources
Market Segment and Sub-Segments
ASIC Proto
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Consumer
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Data Center Cloud (Public, Private, Hybrid)
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Data Center OEM (IHV, ISV, SI, VAR)
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Industrial
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Medical
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Test
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Transportation
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Automotive (Passenger Vehicles)
Transportation Infrastructure (non-charging)