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Configurable HyperBus Flash Memory Controller for HyperFlash/HyperRAM, delivering continuous-burst reads, 0-wait-state write bursts (AXI up to 256 words), AXI-lite control, and device clocks up to 166 MHz for high throughput with a 12-pin low-pin-count interface. Mobiveil’s HyperBus controller is technology-independent, system-validated RTL that interfaces to Spansion/Infineon-style HyperBus devices. It supports true continuous-burst read for HyperFlash, minimum inter-read gaps to maximize read performance, cache-line XiP fetches, 0-wait-state write bursts on the AXI side, and up to 16 outstanding addresses. Deliverables include configurable RTL, HDL testbench, protocol checkers, bus watchers, performance monitors, and design/verification guides.
Mobiveil Inc.
Key Features
- Compatible with spansion hyperbus based memory products
- 0 Wait State Write Burst Operation for HyperBus memory on AXI interface of up to 256 words
- AXI-lite port for control registers accesses
- True Continuous Burst Read operation for HyperFlash on HyperBus memory interface
- Minimum Gap between two Read Operations for highest performance on HyperBus memory interface
- Cache Line accesses for Execution-in-Place (XiP)
- HyperBus memory device clock of upto 166MHz
- Up to 16 outstanding address support in AXI
- Internal FIFO Depths is configurable
- AXI parameters configurable
Offering Brief
Offering Brief
| Device Family | Agilex® 3 FPGA C-Series, Agilex® 5 FPGA D-Series, Agilex® 5 FPGA E-Series, Agilex® 7 FPGA F-Series, Agilex® 7 FPGA I-Series, Agilex® 7 FPGA M-Series, Agilex® 9 FPGA Direct RF-Series, Arria® 10 GT FPGA, Arria® 10 GX FPGA, Arria® 10 SX FPGA, Arria® II GX FPGA, Arria® V GT FPGA, Arria® V GX FPGA, Arria® V GZ FPGA, Arria® V ST FPGA, Arria® V SX FPGA, Cyclone® 10 GX FPGA, Cyclone® 10 LP FPGA, Cyclone® III FPGA, Cyclone® IV E FPGA, Cyclone® IV GX FPGA, Cyclone® V E FPGA, Cyclone® V GT FPGA, Cyclone® V GX FPGA, Cyclone® V SE FPGA, Cyclone® V ST FPGA, Cyclone® V SX FPGA, MAX® 10 FPGA, Stratix® 10 AX FPGA, Stratix® 10 DX FPGA, Stratix® 10 GX FPGA, Stratix® 10 SX FPGA, Stratix® 10 TX FPGA, Stratix® III FPGA, Stratix® IV E FPGA, Stratix® IV GX FPGA, Stratix® V GS FPGA, Stratix® V GX FPGA |
|---|---|
| Offering Status | Production |
| Integrated Testbench | Yes |
| Evaluation License | Yes |
| Latest Quartus Version Supported | 24.3.1 |
| Development Language | Encrypted Verilog, Verilog |
Configurable RTL Code
HDL based test bench and behavioral models
Test cases
Protocol checkers, bus watchers and performance monitors
Design Guide
Verification Guide
Application Note
Ordering Information
NA
from Direct
Documentation & Resources
Market Segment and Sub-Segments
ASIC Proto
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Consumer
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Data Center Cloud (Public, Private, Hybrid)
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Industrial
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Transportation
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Automotive (Passenger Vehicles)
Transportation Infrastructure (non-charging)
