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Highly configurable, low-latency, low-power ApSRAM controller compliant with AXI4 and AP Memory specifications, supporting up to 32 host ports, multi-rank, multi-bank architecture, and advanced power management for SRAM-replacement memory in AI/ML, IoT, automotive, and embedded systems. The Mobiveil ApSRAM Controller is a technology-independent, system-validated IP targeting SRAM-replacement memory (64Mb to 1Gb) located close to the processing unit to act as embedded SRAM (eSRAM). It supports multi-bank/multi-rank architectures, AXI4 system interface (up to 32 ports), APB configuration registers, and multiple QoS arbitration schemes. Features include dynamic power management, self/partial refresh, per-bank refresh, built-in BIST and scan integration, intelligent request scheduling, and look-ahead command processing for high bus efficiency. Delivered with RTL, HDL testbench, protocol checkers, performance monitors, and design/verification/synthesis guides.
Mobiveil Inc.
Key Features
- Compliant with AXI4 specification
- Compliant with AP Memory specification
- Supports memory data width of 64 bits
- Supports APB Interface for configuration registers
- Supports single and multi-port host buses AMBA4 AXI up to 32 ports
- High, medium, normal, port priority
- Built-in asynchronous interface support for DRAM frequencies that are not equal to the AXI frequency
- Separate write and read queues
- The AXI ID signals support out-of-order transactions
- Highly configurable architecture supporting multiple ranks with 8 banks per rank, flexible AXI address width, request queue depth, FIFO sizing, and advanced QoS arbitration schemes for intelligent request scheduling, look-ahead command processing, and bank-level parallelism to maximize bus efficiency.
- Comprehensive memory management features including self-refresh, partial array self-refresh, auto/per-bank refresh, multiple power-down modes (precharge/deep), and built-in Scan/BIST integration for AP Memory devices. Ask ChatGPT
Offering Brief
Offering Brief
| Device Family | Agilex® 3 FPGA C-Series, Agilex® 5 FPGA D-Series, Agilex® 5 FPGA E-Series, Agilex® 7 FPGA F-Series, Agilex® 7 FPGA I-Series, Agilex® 7 FPGA M-Series, Arria® 10 GT FPGA, Arria® 10 GX FPGA, Arria® 10 SX FPGA, Arria® V GT FPGA, Arria® V GX FPGA, Arria® V GZ FPGA, Arria® V ST FPGA, Arria® V SX FPGA, Cyclone® 10 GX FPGA, Cyclone® V GT FPGA, Cyclone® V GX FPGA, Cyclone® V SE FPGA, Cyclone® V ST FPGA, Cyclone® V SX FPGA, Stratix® 10 AX FPGA, Stratix® 10 DX FPGA, Stratix® 10 GX FPGA, Stratix® 10 SX FPGA, Stratix® 10 TX FPGA, Stratix® V GS FPGA, Stratix® V GX FPGA |
|---|---|
| Offering Status | Production |
| Integrated Testbench | Yes |
| Evaluation License | Yes |
| Development Language | Encrypted Verilog, Verilog |
Configurable RTL Code
HDL-based test bench and behavioral models
Test cases
Protocol checkers, bus watchers and performance monitors
Configurable synthesis scripts
Design Guide
Verification Guide
Synthesis Guide
Ordering Information
NA
from Direct
Documentation & Resources
Market Segment and Sub-Segments
ASIC Proto
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Consumer
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Data Center Cloud (Public, Private, Hybrid)
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Data Center OEM (IHV, ISV, SI, VAR)
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Industrial
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Transportation
View Sub-SegmentsTransportation
Automotive (Passenger Vehicles)
Transportation Infrastructure (non-charging)
