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HyperRAM™ controller IP for Winbond devices (x8/x16) with AXI memory-mapped access, APB control, RWDS strobes, linear/wrap/hybrid bursts, low-power modes, and device clocks up to 250 MHz for high bandwidth, low-pin designs. Technology-independent, system-validated RTL that enables smooth integration of Winbond HyperRAM into new-gen SoCs. Supports 8-bit and 16-bit data buses, RWDS read/write data strobes, AXI4 memory-mapped interface for data, APB for control, and linear, wrap, and hybrid bursts. Power features (deep power-down, hybrid sleep) are exposed via control/status registers. Delivered with SV/UVM testbench, behavioral PHY model, and a validated FPGA PHY reference design for rapid bring-up.
Mobiveil Inc.
Key Features
- Compatible with W958D6NW, W958D6NKY, W956x8MBYA, W955D8MBYA HyperRAMTM devices from Winbond.
- 16 bit data bus – DQ[15:0] support for W958D6NW, W958D6NKY devices
- 8 bit data bus – DQ[7:0] support for W956x8MBYA/ W955D8MBYA devices
- Read-Write data strobe RWDS [1:0]
- Memory Clock rate upto 250 MHz
- AXI memory mapped system interface for memory access.
- APB port for control registers accesses.
- Supports Linear Burst, Hybrid burst and Wrap burst
- Low power features like deep power down, Hybrid sleep mode are handled by the controller through a CSR register.
Offering Brief
Offering Brief
| Device Family | Agilex® 3 FPGA C-Series, Agilex® 5 FPGA D-Series, Agilex® 5 FPGA E-Series, Agilex® 7 FPGA F-Series, Agilex® 7 FPGA I-Series, Agilex® 7 FPGA M-Series, Agilex® 9 FPGA Direct RF-Series, Arria® 10 GT FPGA, Arria® 10 GX FPGA, Arria® 10 SX FPGA, Arria® II GX FPGA, Arria® V GT FPGA, Arria® V GX FPGA, Arria® V GZ FPGA, Arria® V ST FPGA, Arria® V SX FPGA, Cyclone® 10 GX FPGA, Cyclone® 10 LP FPGA, Cyclone® III FPGA, Cyclone® IV E FPGA, Cyclone® IV GX FPGA, Cyclone® V E FPGA, Cyclone® V GT FPGA, Cyclone® V GX FPGA, Cyclone® V SE FPGA, Cyclone® V ST FPGA, Cyclone® V SX FPGA, MAX® 10 FPGA, Stratix® 10 AX FPGA, Stratix® 10 DX FPGA, Stratix® 10 GX FPGA, Stratix® 10 SX FPGA, Stratix® 10 TX FPGA, Stratix® III FPGA, Stratix® IV E FPGA, Stratix® IV GX FPGA, Stratix® V GS FPGA, Stratix® V GX FPGA |
|---|---|
| Offering Status | Production |
| Integrated Testbench | Yes |
| Evaluation License | Yes |
| Latest Quartus Version Supported | 24.3.1 |
| Development Language | Encrypted Verilog, Verilog |
RTL Code
System Verilog/UVM based Testbench
Test cases
Behavioral PHY Model
Validated FPGA PHY reference design
Data Sheet
Verification Plan
Ordering Information
NA
from Direct
Documentation & Resources
Market Segment and Sub-Segments
Consumer
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Industrial
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Transportation
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Automotive (Passenger Vehicles)
Transportation Infrastructure (non-charging)
Wireless
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