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Ultra-high-speed OPI PSRAM controller for APMemory UHS devices (x8/x16), with Octal-SPI DDR, AXI4 memory-mapped access (with outstanding addresses), APB control, wrap & continuous burst modes, and device clocks up to 1066 MHz for low-power wearables/IoT and embedded systems. Technology-independent, system-validated RTL that integrates APMemory UHS PSRAM into SoCs/MPUs. Supports AP325608AOKx (8-bit) and AP325616AOKx (16-bit) devices, memory-mapped AXI4 data interface, APB control, DDR OPI transfers, wrap and continuous burst for efficient bandwidth, and an auto-initiate feature to reduce firmware overhead. Low-power controls (Global Reset, Self-Refresh, ZQ Cal) are exposed via CSRs. Package includes RTL, SV/UVM testbench, testcases, protocol checkers/bus watchers, and a reference PHY model for quick bring-up. Synthesis on DC/Genus; simulation on Xcelium/Questa/VCS.
Mobiveil Inc.
Key Features
- Compatible with the following UHS OPI PSRAM devices from APMemory - 8 bit data bus – DQ[7:0] support for AP325608AOKx device - 16 bit data bus – DQ[15:0] support for AP325616AOKx device
- Memory mapped access to the connected PSRAM Device
- Octal SPI Interface with DDR mode access support
- Wrap transfer support
- Continuous mode Burst transfer support for efficient memory access
- Auto-initiate feature to reduce F/W overhead
- AXI4 system interface for memory access with outstanding address support.
- APB port for control registers accesses
- Features like Global Reset, Self Refresh and ZQ Calibration modes control through simple CSR access
- Reference PHY model for easier technology specific integration and implementation
Offering Brief
Offering Brief
| Device Family | Agilex® 3 FPGA C-Series, Agilex® 5 FPGA D-Series, Agilex® 5 FPGA E-Series, Agilex® 7 FPGA F-Series, Agilex® 7 FPGA I-Series, Agilex® 7 FPGA M-Series, Agilex® 9 FPGA Direct RF-Series, Arria® 10 GT FPGA, Arria® 10 GX FPGA, Arria® 10 SX FPGA, Arria® II GX FPGA, Arria® V GT FPGA, Arria® V GX FPGA, Arria® V GZ FPGA, Arria® V ST FPGA, Arria® V SX FPGA, Cyclone® 10 GX FPGA, Cyclone® 10 LP FPGA, Cyclone® III FPGA, Cyclone® IV E FPGA, Cyclone® IV GX FPGA, Cyclone® V E FPGA, Cyclone® V GT FPGA, Cyclone® V GX FPGA, Cyclone® V SE FPGA, Cyclone® V ST FPGA, Cyclone® V SX FPGA, Stratix® 10 AX FPGA, Stratix® 10 DX FPGA, Stratix® 10 GX FPGA, Stratix® 10 SX FPGA, Stratix® 10 TX FPGA, Stratix® III FPGA, Stratix® IV E FPGA, Stratix® IV GX FPGA, Stratix® V GS FPGA, Stratix® V GX FPGA |
|---|---|
| Offering Status | Production |
| Integrated Testbench | Yes |
| Evaluation License | Yes |
| Development Language | Encrypted Verilog, Verilog |
RTL Code
System Verilog/UVM based Testbench
Test cases
Protocol checkers and bus watchers
Design Guide
Verification Guide
Synthesis Guide
Ordering Information
NA
from Direct
Documentation & Resources
Market Segment and Sub-Segments
ASIC Proto
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Consumer
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Industrial
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Medical
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Transportation
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Automotive (Passenger Vehicles)
Transportation Infrastructure (non-charging)
Wireless
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