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Configurable Serial RapidIO (SRIO) controller IP (host/device) compliant with RapidIO spec rev. 4.0 and Error Management Extension rev. 4.0, architected for high link utilization and low latency, with receiver-controlled flow control and packet-oriented user interface. SRIO implements Logical, Transport, and Physical layers, supports serial and parallel interfaces with 1×/2×/4× lanes, internal datapaths 64/128/256-bit, up to 256-byte payloads, PBUS register access, and hardware error recovery with exhaustive reporting. Modes include PIO, DMA, Message, Data-streaming, mixed operation, pass-through for packets to 288 bytes, and “accept-all” failover. Addressing supports 34/50/66-bit with 8/16/32-bit Device IDs. Delivered as configurable RTL with HDL testbench/behavioral models, testcases, protocol checkers, bus watchers, performance monitors, plus configurable synthesis shell and guides. Technology-independent (40 nm ASIC or better, FPGA).
Mobiveil Inc.
Key Features
- Compliant to RapidlO Specifications revision 4.0
- Compliant with RapidlO Error Management Extension specification, Revision 4.0
- Implements Logical, Transport and Physical layers functions
- Architected for high link utilization and low latency
- Efficient receive and transmit buffering scheme
- Implements receiver controlled flow control
- Provides Packet oriented user logic interface
- Supports serial (1x, 2x, 4x) and parallel interfaces, with 64/128/256-bit internal data paths and PBUS interface for configuration register access.
- Handles up to 256-byte payloads, Pass-Through mode for RIO packets up to 288 bytes, and Accept-All mode for failover support.
- Provides 34/50/66-bit addressing with 8/16/32-bit Device ID options.
- Built-in hardware error recovery with exhaustive error reporting and handling.
- PIO, DMA, Message, Data streaming or mixed mode of operation, Parallel/Serial mode of operation, Bypass support
Offering Brief
Offering Brief
| Device Family | Arria® 10 GT FPGA, Arria® 10 GX FPGA, Arria® 10 SX FPGA, Arria® II GX FPGA, Arria® V GT FPGA, Arria® V GX FPGA, Arria® V GZ FPGA, Arria® V ST FPGA, Arria® V SX FPGA, Cyclone® 10 GX FPGA, Cyclone® IV GX FPGA, Cyclone® V GT FPGA, Cyclone® V GX FPGA, Cyclone® V ST FPGA, Cyclone® V SX FPGA, Stratix® 10 AX FPGA, Stratix® 10 DX FPGA, Stratix® 10 GX FPGA, Stratix® 10 SX FPGA, Stratix® 10 TX FPGA, Stratix® IV GX FPGA, Stratix® V GS FPGA, Stratix® V GX FPGA |
|---|---|
| Offering Status | Production |
| Integrated Testbench | Yes |
| Evaluation License | Yes |
| Latest Quartus Version Supported | 24.3.1 |
| Development Language | Encrypted Verilog, Verilog |
Configurable RTL Code
HDL based test bench and behavioral models
Test cases
Protocol checkers, bus watchers and performance monitors
Configurable synthesis shell
Design Guide
Verification Guide
Synthesis Guide
Ordering Information
NA
from Direct
Documentation & Resources
Market Segment and Sub-Segments
Aerospace
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ASIC Proto
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Data Center Cloud (Public, Private, Hybrid)
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Data Center OEM (IHV, ISV, SI, VAR)
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Industrial
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Transportation
View Sub-SegmentsTransportation
Automotive (Passenger Vehicles)
Transportation Infrastructure (non-charging)
