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The EtherCAT Master IP is a high-performance IP for SoC FPGAs that significantly reduces software load, allowing more users flexible utilization. The FPGA hardware-based communication engine achieves high-speed communication intervals and stable communication cycles, thus reducing the software load. This enables the allocation of more CPU processing resources to applications, and software load fluctuations (including the addition of functions) do not affect communication. Furthermore, the IP format allows for "direct" integration onto your own board.
NDR Co.,LTD.
Key Features
- High-Speed EtherCAT Master IP, Reduces CPU load and achieves high-precision control.
- Supports Altera FPGA, enabling flexible system configuration.
- Provision of APIs and sample software contributes to shortening development time.
Offering Brief
Offering Brief
| Device Family | Agilex® 3 FPGA C-Series, Agilex® 5 FPGA E-Series, Cyclone® V E FPGA, Cyclone® V GT FPGA, Cyclone® V GX FPGA, Cyclone® V SE FPGA, Cyclone® V ST FPGA, Cyclone® V SX FPGA, MAX® 10 FPGA |
|---|---|
| Offering Status | Production |
| Latest Quartus Version Supported | 23.1.1 |
| Development Language | C/C++, Encrypted VHDL |
Documentation
Sample Project
Ordering Information
N-EMB-800
from NDR
