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The PTP Hybrid Clock (HC) from NetTimeLogic is a combination of NetTimeLogic's PTP Transparent Clock (TC) and PTP Ordinary Clock (OC) according to IEEE1588-2019 (PTP). It is intended mainly for daisy-chain applications but can also wrap other non-deterministic Ethernet cores/devices like Bridges, Switches, or Redundancy Nodes, and runs the whole protocol handling, algorithms, and calculations are implemented in the core, no CPU is required, which allows running PTP synchronization completely independent and standalone. The HC can run again as Master or Slave with E2E or P2P as delay mechanism and supports the following PTP Profiles: Default Profile, Power Profile, Utility Profile, TSN Profile (802.1AS) and ITU Profiles (ITU-T-G82651/G82751/G82752)
NetTimeLogic GmbH
Key Features
- Combined PTP Ordinary Clock and PTP Transparent Clock according to IEEE1588-2019/2008
- Two (TC) plus one (OC) Port, used for daisy chaining or redundancy protocols, Full line speed
- Support for Default Profile: Layer 2 (Ethernet) and Layer 3 (Ip) support
- Support for Power Profile: C37.238-2011 and C37.238-2017 including VLAN support
- Support for Utility Profile: including HSR and PRP tag handling
- Support for IEEE802.1AS-REV: including IEEE802.1CB tag handling
- Support for ITU Profiles : ITUG82651, ITUG82751, ITUG82752, up to 4096 Unicast Slaves at 128 frames/s
- One Step and Two Step support
- Peer to Peer (P2P) and End to End (E2E) delay measurement
- Master and Slave support
- Optional Management and Signaling Message support
- AXI4 Light register set or static configuration
Offering Brief
Offering Brief
| Device Family | Agilex® 3 FPGA C-Series, Agilex® 5 FPGA D-Series, Agilex® 5 FPGA E-Series, Agilex® 7 FPGA F-Series, Agilex® 7 FPGA I-Series, Agilex® 7 FPGA M-Series, Agilex® 9 FPGA Direct RF-Series, Arria® 10 GT FPGA, Arria® 10 GX FPGA, Arria® 10 SX FPGA, Arria® V GT FPGA, Arria® V GX FPGA, Arria® V GZ FPGA, Arria® V ST FPGA, Arria® V SX FPGA, Cyclone® 10 GX FPGA, Cyclone® 10 LP FPGA, Cyclone® IV E FPGA, Cyclone® IV GX FPGA, Cyclone® V E FPGA, Cyclone® V GT FPGA, Cyclone® V GX FPGA, Cyclone® V SE FPGA, Cyclone® V ST FPGA, Cyclone® V SX FPGA, MAX® 10 FPGA, Stratix® 10 AX FPGA, Stratix® 10 DX FPGA, Stratix® 10 GX FPGA, Stratix® 10 SX FPGA, Stratix® 10 TX FPGA, Stratix® IV E FPGA, Stratix® IV GX FPGA, Stratix® V GS FPGA, Stratix® V GX FPGA |
|---|---|
| Offering Status | Production |
| Integrated Testbench | Yes |
| Evaluation License | Yes |
| Design Examples Available | Yes |
| Intertop | ISPCS, IIC |
| Latest Quartus Version Supported | 25.1.0 |
| OS Support | Not required |
| Development Language | VHDL |
Source Code
Ordering Information
NTL_PTP_HC
from Direct
Documentation & Resources
Market Segment and Sub-Segments
Access
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Aerospace
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Broadcast
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Data Center Cloud (Public, Private, Hybrid)
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Defense
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Government
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Test
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Transportation
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Automotive (Passenger Vehicles)
Non-Automotive Transportation
Transportation Infrastructure (non-charging)
