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NetTimeLogic’s PTP Timestamp Unit (TSU) is an implementation of a single port Frame Timestamp Unit according to IEEE1588-2019/2008 (PTP). It detects PTP frames on the (R)(G)MII (tap or intercept) and timestamps PTP event frames and provides them delay compensated to a PTP Software stack (e.g. PTPd, PTP4l, etc…) and can also insert timestmaps into PTP frames for one-step mode. The Timestamp Unit can be used to build a PTP Ordinary Clock (OC) as Master and Slave; it can also be used to build a PTP Boundary Clock (BC) by having multiple instances of the IP core connected to multiple Ethernet ports.
NetTimeLogic GmbH
Key Features
- PTP Timestamp Unit according to IEEE1588-2019/2008
- PTP frame detection and PTP event frame timestamping
- Taps path between MAC and PHY or intercepts path between MAC and PHY, Full line speed
- Optional One Step support (requires intercepting the path between MAC and PHY)
- Support for Layer 2 (Ethernet) and Layer 3 (Ip), VLAN, HSR and PRP, Peer to Peer (P2P) and End to End (E2E).
- Master and Slave support
- Configurable Interrupt
- Optional 10G XGMII extension (requires add-on license)
- Linux Driver, TSU driver part is independent from MAC driver (needs to be called though from the MAC driver)
- PHY Delay compensation with automatic link speed detection
Offering Brief
Offering Brief
| Device Family | Agilex® 3 FPGA C-Series, Agilex® 5 FPGA D-Series, Agilex® 5 FPGA E-Series, Agilex® 7 FPGA F-Series, Agilex® 7 FPGA I-Series, Agilex® 7 FPGA M-Series, Agilex® 9 FPGA Direct RF-Series, Arria® 10 GT FPGA, Arria® 10 GX FPGA, Arria® 10 SX FPGA, Arria® V GT FPGA, Arria® V GX FPGA, Arria® V GZ FPGA, Arria® V ST FPGA, Arria® V SX FPGA, Cyclone® 10 GX FPGA, Cyclone® 10 LP FPGA, Cyclone® IV E FPGA, Cyclone® IV GX FPGA, Cyclone® V E FPGA, Cyclone® V GT FPGA, Cyclone® V GX FPGA, Cyclone® V SE FPGA, Cyclone® V ST FPGA, Cyclone® V SX FPGA, MAX® 10 FPGA, Stratix® 10 AX FPGA, Stratix® 10 DX FPGA, Stratix® 10 GX FPGA, Stratix® 10 SX FPGA, Stratix® 10 TX FPGA, Stratix® IV E FPGA, Stratix® IV GX FPGA, Stratix® V GS FPGA, Stratix® V GX FPGA |
|---|---|
| Offering Status | Production |
| Integrated Testbench | Yes |
| Evaluation License | Yes |
| Design Examples Available | Yes |
| Intertop | ISPCS, IIC |
| Latest Quartus Version Supported | 25.1.0 |
| Development Language | C/C++, VHDL |
Source Code, Driver
Ordering Information
NTL_PTP_TSU
from Direct
Documentation & Resources
Market Segment and Sub-Segments
Access
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Aerospace
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Broadcast
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Data Center Cloud (Public, Private, Hybrid)
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Defense
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Government
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Test
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Transportation
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Automotive (Passenger Vehicles)
Non-Automotive Transportation
Transportation Infrastructure (non-charging)
