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The TSN Network Core (Switched End Node) from NetTimeLogic is a standalone Time-Sensitive Networking (TSN) core according to IEEE 802.1, IEEE 1588, and IEC 62439-3 standards. It supports TSN features like time synchronization, scheduling, priority queues, network redundancy, credit-based shaping, cyclic forwarding, and preemption completely in hardware, which allows running TSN protocols completely independent and standalone from the user application. It can run as a redundant endpoint, bridge between a redundant and a non-redundant network, or daisy chain node.
NetTimeLogic GmbH
Key Features
- Up to 8 different priority queues, with freely definable VLAN priorities
- Up to 64 phases per cycle according to priority queues
- Cycle time and phase durations freely configurable (max 1 ms, min 15.625 us)
- Cut-Through (<2us delay @ 1G) or Store-And-Forward frame forwarding
- Frame scheduling according to IEEE 802.1 Qbv, Cyclic forwarding according to IEEE 802.1 Qch, Credit based shaper according to IEEE 802.1 Qav, Frame preemption according to IEEE 802.1 Qbu and IEEE 802.3 br can be enabled for the lowest priority to allow maximum bandwidth usage
- Synchronization with sub-microsecond accuracy according to IEEE 1588 Default-, Utility- or Power-Profile or according to IEEE 802.1 AS
- Supports the HSR and PRP redundancy protocol according to IEC 62439-3 rev 3 with hardware supervision handling and the Frame Replication & Elimination for Reliability (FRER) according to IEEE 802.1 CB
- Can run as Dual Attached Node (DAN) or as Redundancy Box (RedBox) or Daisy Chain Node
- Two forwarding ports, one internal/interlink port. Interlink port is optional when AXI stream interfaces are used
- Supports up to 8 AXI streaming interfaces, one for each priority/phase
- Full line speed
- AXI4 Light register set or static configuration
Offering Brief
Offering Brief
| Device Family | Agilex® 3 FPGA C-Series, Agilex® 5 FPGA D-Series, Agilex® 5 FPGA E-Series, Agilex® 7 FPGA F-Series, Agilex® 7 FPGA I-Series, Agilex® 7 FPGA M-Series, Agilex® 9 FPGA Direct RF-Series, Arria® 10 GT FPGA, Arria® 10 GX FPGA, Arria® 10 SX FPGA, Arria® V GT FPGA, Arria® V GX FPGA, Arria® V GZ FPGA, Arria® V ST FPGA, Arria® V SX FPGA, Cyclone® 10 GX FPGA, Cyclone® 10 LP FPGA, Cyclone® III FPGA, Cyclone® IV E FPGA, Cyclone® IV GX FPGA, Cyclone® V E FPGA, Cyclone® V GT FPGA, Cyclone® V GX FPGA, Cyclone® V SE FPGA, Cyclone® V ST FPGA, Cyclone® V SX FPGA, MAX® 10 FPGA, Stratix® 10 AX FPGA, Stratix® 10 DX FPGA, Stratix® 10 GX FPGA, Stratix® 10 SX FPGA, Stratix® 10 TX FPGA, Stratix® IV E FPGA, Stratix® IV GX FPGA, Stratix® V GS FPGA, Stratix® V GX FPGA |
|---|---|
| Offering Status | Production |
| Integrated Testbench | Yes |
| Evaluation License | Yes |
| Design Examples Available | Yes |
| Intertop | IIC |
| Latest Quartus Version Supported | 25.1.0 |
| OS Support | Not Required |
| Development Language | VHDL |
Source Code
Ordering Information
NTL_RED_TSN
from Direct
Documentation & Resources
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