NetTimeLogic’s Time Of Day (TOD) Master Clock is a full hardware (FPGA) only implementation of a synchronization core able to synchronize a Time of Day sink via NMEA over UART. The whole message creation, algorithms and calculations are implemented in the core, no CPU is required. This allows running TOD synchronization completely independent and standalone from the user application.
NetTimeLogic GmbH
Key Features
- Time of Day Master Clock
- Built-in UART transmitter with configurable baud rate
- NMEA message creator
- Support for NMEA GPZDA and RMC messages for time distribution
- Hardware time conversion from seconds since midnight 1.1.1970 (Linux, TAI, PTP) into Time of Day format (hh:mm:ss dd:mm:yyyy)
- Sending at the local second overflow
- Local time can be set via registers
- AXI4 Light register set or static configuration
Offering Brief
Offering Brief
| Device Family | Agilex® 3 FPGA C-Series, Agilex® 5 FPGA D-Series, Agilex® 5 FPGA E-Series, Agilex® 7 FPGA F-Series, Agilex® 7 FPGA I-Series, Agilex® 7 FPGA M-Series, Agilex® 9 FPGA Direct RF-Series, Arria® 10 GT FPGA, Arria® 10 GX FPGA, Arria® 10 SX FPGA, Arria® V GT FPGA, Arria® V GX FPGA, Arria® V GZ FPGA, Arria® V ST FPGA, Arria® V SX FPGA, Cyclone® 10 GX FPGA, Cyclone® 10 LP FPGA, Cyclone® IV E FPGA, Cyclone® IV GX FPGA, Cyclone® V E FPGA, Cyclone® V GT FPGA, Cyclone® V GX FPGA, Cyclone® V SE FPGA, Cyclone® V ST FPGA, Cyclone® V SX FPGA, MAX® 10 FPGA, Stratix® 10 AX FPGA, Stratix® 10 DX FPGA, Stratix® 10 GX FPGA, Stratix® 10 SX FPGA, Stratix® 10 TX FPGA, Stratix® IV E FPGA, Stratix® IV GX FPGA, Stratix® V GS FPGA, Stratix® V GX FPGA |
|---|---|
| Offering Status | Production |
| Integrated Testbench | Yes |
| Evaluation License | Yes |
| Design Examples Available | Yes |
| Intertop | ISPCS, IIC |
| Latest Quartus Version Supported | 25.1.0 |
| OS Support | Not required |
| Development Language | VHDL |
Source Code
Ordering Information
NTL_TOD_MASTER
from Direct
Documentation & Resources
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