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NetTimeLogic’s Time Of Day (TOD) Slave Clock is a full hardware (FPGA) only implementation of a synchronization core able to synchronize to a Time of Day source via NMEA, UBX, TSIP or ESIPover UART. The whole interface handling, message parsing, algorithms and calculations are implemented in the core, no CPU is required. This allows running TOD synchronization completely independent and standalone from the user application.
NetTimeLogic GmbH
Key Features
- Time of Day Slave Clock
- Built-in UART receiver with configurable baudrate
- NMEA message parser
- Support for UBX (uBlox®), TSIP (Trimble®), ESIP (Furuno® GT88) and PFEC (Furuno® GT100) protocol
- Support for GPS, GLONASS, GALILEO, BEIDOU or Combined GNSS
- Supports NMEA GxZDA, GxRMC, GxGSA, GxGSV and GxGGA messages
- Optional support for OCP NMEA GxUTC message for UTC information and handling
- UTC handling and additional Status information for UBX, TSIP, ESIP and PFEC
- Quality supervision and filtering of GxRMC messages
- Hardware time conversion from Time of Day format (hh:mm:ss dd:mm:yyyy) into seconds since midnight 1.1.1970 (Linux, TAI, PTP)
- In UBX/TSIP/ESIP/PFEC mode provides Current UTC offset to TAI and Leap Second information
- AXI4Lite register set or static configuration
Offering Brief
Offering Brief
| Device Family | Agilex® 3 FPGA C-Series, Agilex® 5 FPGA D-Series, Agilex® 5 FPGA E-Series, Agilex® 7 FPGA F-Series, Agilex® 7 FPGA I-Series, Agilex® 7 FPGA M-Series, Agilex® 9 FPGA Direct RF-Series, Arria® 10 GT FPGA, Arria® 10 GX FPGA, Arria® 10 SX FPGA, Arria® V GT FPGA, Arria® V GX FPGA, Arria® V GZ FPGA, Arria® V ST FPGA, Arria® V SX FPGA, Cyclone® 10 GX FPGA, Cyclone® 10 LP FPGA, Cyclone® IV E FPGA, Cyclone® IV GX FPGA, Cyclone® V E FPGA, Cyclone® V GT FPGA, Cyclone® V GX FPGA, Cyclone® V SE FPGA, Cyclone® V ST FPGA, Cyclone® V SX FPGA, MAX® 10 FPGA, Stratix® 10 AX FPGA, Stratix® 10 DX FPGA, Stratix® 10 GX FPGA, Stratix® 10 SX FPGA, Stratix® 10 TX FPGA, Stratix® IV E FPGA, Stratix® IV GX FPGA, Stratix® V GS FPGA, Stratix® V GX FPGA |
|---|---|
| Offering Status | Production |
| Integrated Testbench | Yes |
| Evaluation License | Yes |
| Design Examples Available | Yes |
| Latest Quartus Version Supported | 25.1.0 |
| OS Support | Not required |
| Development Language | VHDL |
Source Code
Ordering Information
NTL_TOD_SLAVE
from Direct
Documentation & Resources
Market Segment and Sub-Segments
Access
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Aerospace
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Broadcast
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Data Center Cloud (Public, Private, Hybrid)
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Defense
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Government
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Test
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Transportation
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Automotive (Passenger Vehicles)
Non-Automotive Transportation
Transportation Infrastructure (non-charging)
